Maulik V Vaghela dba6c4cfc0 soc/intel/tigerlake: Update FSP params for Jasper Lake ... Update FSP parameters for various configurations like: - graphics - USB - PCIe root ports - SD card - eMMC - Audio - Basic UART configuration These are the initial settings for JSL. This patch also corrects the debug_interface_flag definitions. TEST=Build dedede board Change-Id: Ia8e88f92989fe40d7bd1c28947e005cc0d862fcb Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>		2020-02-27 12:03:42 +00:00
..
amd	soc/amd/common/block/include/amdblocks: Fix typos	2020-02-24 13:01:03 +00:00
cavium
intel	soc/intel/tigerlake: Update FSP params for Jasper Lake	2020-02-27 12:03:42 +00:00
mediatek	treewide: capitalize 'USB'	2020-02-26 17:06:40 +00:00
nvidia	commonlib: Add commonlib/bsd	2020-01-28 06:36:13 +00:00
qualcomm	sc7180: clock: Fix QUP DFSR configuration for perf levels	2020-02-07 23:12:00 +00:00
rockchip	soc/rockchip: Fix typos	2020-02-24 13:04:02 +00:00
samsung	soc/{samsung,sifive}: Fix typos	2020-02-24 13:01:15 +00:00
sifive	soc/{samsung,sifive}: Fix typos	2020-02-24 13:01:15 +00:00
ucb