Eric Lai de2ab41fc4 soc/intel/common: Move L1_substates_control to pcie_rp.h ... L1_substates_control is common define. Move out of soc level. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I54574b606985e82d00beb1a61cce3097580366a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/49295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>		2021-01-18 07:28:32 +00:00
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acpi	soc/intel/common: Move gfx.asl to drivers/intel/gma	2020-12-30 16:35:21 +00:00
bootblock	soc/intel/alderlake: Add PCH ID 0x5182	2021-01-12 05:18:51 +00:00
include/soc	soc/intel/alderlake: Add SPI DMI Destination ID	2020-12-23 03:28:47 +00:00
romstage	soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs	2021-01-10 17:49:19 +00:00
acpi.c	soc/intel: Rename to soc_fill_gnvs()	2021-01-10 11:40:22 +00:00
chip.c	soc/intel: hook up new gpio device in the soc chips	2020-12-30 00:30:04 +00:00
chip.h	soc/intel/common: Move L1_substates_control to pcie_rp.h	2021-01-18 07:28:32 +00:00
chipset.cb	soc/intel: hook up new gpio device in the soc chips	2020-12-30 00:30:04 +00:00
cpu.c	soc/intel: deduplicate ACPI timer emulation	2020-10-28 21:28:19 +00:00
elog.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
espi.c	soc/intel: Drop dev parameter from soc_get_gen_io_dec_range()	2021-01-08 08:23:59 +00:00
finalize.c	soc/intel/*: drop useless XTAL shutdown qualification code	2020-10-19 07:09:12 +00:00
fsp_params.c	soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs	2021-01-10 17:49:19 +00:00
gpio.c	soc/intel/alderlake: Add GPIOs for Alder Lake SOC	2020-09-27 03:03:25 +00:00
gspi.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
i2c.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
Kconfig	soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs	2021-01-10 17:49:19 +00:00
lockdown.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
Makefile.inc	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
me.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
meminit.c	soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration	2020-11-29 14:39:06 +00:00
p2sb.c	soc/intel/alderlake/romstage: Do initial SoC commit till romstage	2020-09-15 15:13:50 +00:00
pmc.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
pmutil.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
reset.c	soc/intel: Use of common reset code block	2020-11-02 10:43:53 +00:00
smihandler.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
smmrelocate.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
soundwire.c	mb/intel: Enable ALC711 Audio codec over SNDW0 link	2020-11-07 08:55:53 +00:00
spi.c	soc/intel/alderlake: Add SPI DMI Destination ID	2020-12-23 03:28:47 +00:00
systemagent.c	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	2020-10-03 12:15:22 +00:00
uart.c	soc/intel: rename uart_max_index	2021-01-12 23:38:32 +00:00