df7aecd926
Some CPUs, (Intel core2 and pineview) have slightly different SMRR MTRR mechanism. The MSR_SMRR_PHYSBASE/MASK MSRs are at a different location, have slightly different semantics and need SMRR enable in a locked down IA32_FEATURE_CONTROL MSR. This change takes away the possibility to (not) lock IA32_FEATURE_CONTROL on these CPUs, as this is needed for SMRR MSR to work. Since sockets cover multiple CPUs of which only some support SMRR, the Kconfig option CONFIG_SET_IA32_FC_LOCK_BIT is kept in place, even though it gets meaningless on those CPUs. Locking that bit was the default anyway. With this patch Intel Netburst CPUs also configure IA32_FEATURE_CONTROL. According to Intel 64 and IA-32 Architectures Software Developer's Manual those CPUs support that MSR so issues are not to be expected. Change-Id: Ia85602e75385e24ebded75e6e6dd38ccc969a76b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/27586 Tested-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Martin Roth <martinroth@google.com> |
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.. | ||
car | ||
common | ||
fit | ||
fsp_model_406dx | ||
haswell | ||
hyperthreading | ||
microcode | ||
model_6bx | ||
model_6dx | ||
model_6ex | ||
model_6fx | ||
model_6xx | ||
model_65x | ||
model_67x | ||
model_68x | ||
model_69x | ||
model_106cx | ||
model_206ax | ||
model_1067x | ||
model_2065x | ||
model_f2x | ||
model_f3x | ||
model_f4x | ||
slot_1 | ||
smm/gen1 | ||
socket_441 | ||
socket_BGA956 | ||
socket_BGA1284 | ||
socket_FCBGA559 | ||
socket_LGA775 | ||
socket_mFCPGA478 | ||
socket_mPGA478 | ||
socket_mPGA478MN | ||
socket_mPGA604 | ||
speedstep | ||
thermal_monitoring | ||
turbo | ||
Kconfig | ||
Makefile.inc |