Aaron Durbin e35e695377 soc/intel/common/lpss_i2c: correct bus speed error ... The wrong value was used for reporting an error when a requested bus speed was made that isn't supported. Use the requested value. Change-Id: I6c92ede3d95590d95a42b40422bab88ea9ae72a1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17474 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>		2016-11-19 16:56:23 +01:00
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apollolake	soc/intel/apollolake: Enable and Lock AES feature register	2016-11-17 15:18:47 +01:00
baytrail	intel post-car: Increase stacktop alignment	2016-11-18 20:59:12 +01:00
braswell	intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZE	2016-11-08 19:16:24 +01:00
broadwell	intel post-car: Increase stacktop alignment	2016-11-18 20:59:12 +01:00
common	soc/intel/common/lpss_i2c: correct bus speed error	2016-11-19 16:56:23 +01:00
fsp_baytrail	intel/fsp_baytrail: Fix assignment of PcdeMMCBootMode	2016-11-16 18:23:11 +01:00
fsp_broadwell_de	soc/intel/fsp_broadwell_de: Fix system hang when timestamp is enabled	2016-10-09 19:08:07 +02:00
quark	soc/intel/quark: Fix FSP 2.0 build	2016-09-30 01:16:51 +02:00
sch	src/soc: Remove unnecessary whitespace before "\n" and "\t"	2016-08-28 18:25:14 +02:00
skylake	skylake: Update the thermal time window for throttling action	2016-11-14 17:20:38 +01:00