coreboot-kgpe-d16/src/northbridge/intel/x4x
Kyösti Mälkki e39becf521 intel/cpu: Switch older models to TSC_MONOTONIC_TIMER
The implementation of udelay() with LAPIC timers
existed first, as we did not have calculations
implemented for TSC frequency.

Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-09-24 22:56:52 +00:00
..
acpi Remove DEFAULT_PCIEXBAR alias 2019-03-06 11:54:17 +00:00
acpi.c nb/northbridge/intel/x4x/acpi.c: Remove variable set but not used 2019-05-24 09:35:46 +00:00
bootblock.c
chip.h
dq_dqs.c src/northbridge/intel: Remove unused variables 2019-04-25 15:54:07 +00:00
early_init.c nb/intel/x4x/early_init.c: Remove variable set but not used 2019-05-23 08:56:30 +00:00
gma.c src/northbridge: Add missing 'include <types.h>' 2019-05-29 20:28:27 +00:00
iomap.h Remove DEFAULT_PCIEXBAR alias 2019-03-06 11:54:17 +00:00
Kconfig intel/cpu: Switch older models to TSC_MONOTONIC_TIMER 2019-09-24 22:56:52 +00:00
Makefile.inc northbridge/intel: Rename ram_calc.c to memmap.c 2019-08-07 05:42:15 +00:00
memmap.c intel/smm/gen1: Use smm_subregion() 2019-08-28 22:51:27 +00:00
northbridge.c intel/smm/gen1: Rename header file 2019-08-15 06:53:52 +00:00
raminit.c nb/x4x: Rename {ddr,fsb}2{mhz,ps} as {ddr,fsb}_to_{mhz,ps} 2019-06-21 08:54:13 +00:00
raminit_ddr23.c nb/intel/x4x/raminit: Move dummy reads after JEDEC init 2019-09-06 00:15:02 +00:00
raminit_tables.c
rcven.c nb/intel/x4x/rcven.c: Remove variable set but not used 2019-06-04 13:18:14 +00:00
x4x.h nb/x4x: Rename {ddr,fsb}2{mhz,ps} as {ddr,fsb}_to_{mhz,ps} 2019-06-21 08:54:13 +00:00