Saurabh Satija e46dbcc53a soc/apollolake: Allow enable/disable of LPSS S0ix from devicetree ... Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784 Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/15055 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)		2016-07-02 03:33:52 +02:00
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broadcom/cygnus	soc/*: fix uart's regwidth specification in cbtables	2016-02-21 12:26:05 +01:00
dmp/vortex86ex	dmp/vortex86ex: Merge northbridge and southbridge into soc	2016-05-05 20:06:33 +02:00
imgtec/pistachio	drivers/uart: Use uart_platform_refclk for all UART models	2016-05-09 18:45:44 +02:00
intel	soc/apollolake: Allow enable/disable of LPSS S0ix from devicetree	2016-07-02 03:33:52 +02:00
marvell	drivers/uart: Use uart_platform_refclk for all UART models	2016-05-09 18:45:44 +02:00
mediatek/mt8173	mt8173: dram: Add more sample points to improve dram timing margin	2016-06-12 12:13:10 +02:00
nvidia	tegra124: Actually align the framebuffer's bytes-per-line to 32	2016-06-28 17:54:36 +02:00
qualcomm	Gale board: Move TPM setup function to verstage.c	2016-06-02 00:19:11 +02:00
rdc/r8610	rdc/r8610: Move to src/soc	2016-05-05 20:08:58 +02:00
rockchip	rk3399: clean up sdram controller initialization code	2016-06-24 20:53:25 +02:00
samsung	region: Add writeat and eraseat support	2016-06-24 20:48:12 +02:00
ucb/riscv	tree: drop last paragraph of GPL copyright header	2015-10-31 21:37:39 +01:00