coreboot-kgpe-d16/src
Kyösti Mälkki e76ce871c8 arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limits
With top-aligned bootblock this is no longer globally needed.
The default maximum is now a generous 256 KiB with couple
platforms having lower limits of 32 KiB and 64 KiB.

Change-Id: Ib1aee44908c0dcbc17978d3ee53bd05a6200410c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-01-28 08:55:31 +00:00
..
acpi ACPI: Add top-level ASL 2021-01-27 15:35:13 +00:00
arch arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limits 2021-01-28 08:55:31 +00:00
commonlib
console
cpu arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limits 2021-01-28 08:55:31 +00:00
device src/device: Don't die() on vBIOS errors 2021-01-27 10:24:44 +00:00
drivers cpu/x86: Rename __protected_start symbol 2021-01-28 08:53:30 +00:00
ec ec/google/wilco: Convert to ASL 2.0 syntax 2021-01-24 21:51:39 +00:00
include ACPI: Separate device_nvs_t 2021-01-27 10:25:03 +00:00
lib arch/x86: Top-align .init in bootblock 2021-01-28 08:54:21 +00:00
mainboard arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limits 2021-01-28 08:55:31 +00:00
northbridge nb/intel/haswell/haswell.h: Do not include pch.h 2021-01-27 21:28:18 +00:00
security security/tpm/tss/tcg-1.2/tss.c: Use __func__ 2021-01-19 08:58:50 +00:00
soc arch/x86: Remove most C_ENV_BOOTBLOCK_SIZE limits 2021-01-28 08:55:31 +00:00
southbridge nb/intel/haswell/haswell.h: Do not include pch.h 2021-01-27 21:28:18 +00:00
superio
vendorcode soc/amd/picasso: Add UPDs for support eDP power sequence adjust 2021-01-25 09:10:51 +00:00
Kconfig