coreboot-kgpe-d16/src/soc/imgtec/pistachio
Ionela Voinescu e7a336ac29 mips: add coherency argument to identity mapping
In order for a U-boot payload to work properly the soc_registers
region (device registers) needs to be mapped as uncached.
Therefore, add a coherency argument to the identity mapping funcion
which will establish the type of mapping.

Change-Id: I26fc546378acda4f4f8f4757fbc0adb03ac7db9f
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12769
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-12-29 18:02:15 +01:00
..
include/soc mainboard/google/urara: change SYS PLL to 700MHz 2015-12-27 20:55:21 +01:00
bootblock.c mips: add coherency argument to identity mapping 2015-12-29 18:02:15 +01:00
cbmem.c tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
clocks.c mainboard/google/urara: change SYS PLL to 700MHz 2015-12-27 20:55:21 +01:00
ddr2_init.c imgtec/pistachio: DDR2, DDR3: DLL reset set 2015-12-21 02:06:12 +01:00
ddr3_init.c imgtec/pistachio: DDR2, DDR3: DLL reset set 2015-12-21 02:06:12 +01:00
Kconfig Drop src/cpu/ indirection for MIPS 2015-12-17 21:25:31 +01:00
Makefile.inc soc/imgtec/pistachio: Implement hard_reset() 2015-12-17 21:13:35 +01:00
monotonic_timer.c tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
reset.c soc/imgtec/pistachio: add implementation for system reset 2015-12-17 21:13:57 +01:00
romstage.c tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
soc.c tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
spi.c pistachio: sort included header files 2015-06-10 22:21:55 +02:00
uart.c tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00