coreboot-kgpe-d16/src/soc
Kilari Raasi ebb28c523e soc/intel/meteorlake: Disable MarginLimitCheck and RMC UPDs
By default MarginLimitCheck and RMC UPDs are enabled in FSP
which enables fast and cold boot retraining causing the
boot time increase. So, disabling the same UPDs to fix it.

Change-Id: Ib15d37dbe177f31590f23de4e239a2e82abf1335
Signed-off-by: Kilari Raasi <kilari.raasi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-11 05:06:18 +00:00
..
amd soc/amd/common: Move PCIe CLKREQ programming under fsp 2023-12-06 19:12:59 +00:00
cavium Revert "Kconfig: Bring HEAP_SIZE to a common, large value" 2023-11-07 17:35:39 +00:00
example/min86 soc: Remove SOC_SPECIFIC_OPTIONS 2023-08-21 23:45:43 +00:00
intel soc/intel/meteorlake: Disable MarginLimitCheck and RMC UPDs 2023-12-11 05:06:18 +00:00
mediatek soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S 2023-12-04 16:48:33 +00:00
nvidia memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 2023-10-11 12:08:22 +00:00
qualcomm qualcomm/sc7180: Move QCSDI and increase romstage size by 4KB 2023-11-18 00:41:53 +00:00
rockchip fmap: Map less space in fallback path without CBFS verification 2023-11-13 14:19:01 +00:00
samsung memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 2023-10-11 12:08:22 +00:00
sifive/fu540 memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere 2023-10-11 12:08:22 +00:00
ti
ucb/riscv