coreboot-kgpe-d16/src/soc/intel
Duncan Laurie edb55fc0ad broadwell: Fix GPE register addresses
This macro is incorrect and should be counting by dword instead of byte.
The effects of this were subtle: incorrect events in ELOG and hanging when
waking from USB input because PME_B0 was not disabled properly.

BUG=chrome-os-partner:31611
BRANCH=none
TEST=test wake from suspend with USB keyboard

Original-Change-Id: I7caf1d46283071787550a9765703897181774957
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/214258
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 3cfc4a1812466cb1c1317b8f21321aafee623857)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I3e2f8190d824692ecb961615becf65319a6ffd8b
Reviewed-on: http://review.coreboot.org/8965
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2015-03-27 06:24:20 +01:00
..
baytrail bootstate: use structure pointers for scheduling callbacks 2015-03-18 16:41:43 +01:00
broadwell broadwell: Fix GPE register addresses 2015-03-27 06:24:20 +01:00
common bootstate: use structure pointers for scheduling callbacks 2015-03-18 16:41:43 +01:00
fsp_baytrail intel/fsp_baytrail: Add PCI Root Port IRQ Routing 2015-03-12 20:35:49 +01:00
Kconfig broadwell: Hook into the build system 2014-12-31 21:23:09 +01:00
Makefile.inc broadwell: Hook into the build system 2014-12-31 21:23:09 +01:00