Maulik V Vaghela e6e8b3d337 soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO ... Adding GPIO definition for community 3 which is CPU reserved GPIO used by CPU side PCIe root ports. We did not have this definition since FSP used to program this GPIOs. Now, instead of FSP, coreboot programs CPU PCIe GPIOs for CLKSRC and lanes to put GPIOs in native mode. Thus adding definition of this virtual GPIOs in this CL. BUG=None BRANCH=None TEST=Check if correct registers are being programmed Change-Id: I481ea7e3ba948bf6d37b97d08c675a18ee68125d Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52783 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2021-05-05 22:41:41 +00:00
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amd	soc/amd/cezanne/agesa_acpi: add add_agesa_fsp_acpi_table call	2021-05-05 21:43:34 +00:00
cavium
example	arch/x86: Move prologue to .init section	2021-01-07 11:02:03 +00:00
intel	soc/intel/alderlake: Add GPIO definition for CPU PCIe vGPIO	2021-05-05 22:41:41 +00:00
mediatek	soc/mediatek/mt8192: devapc: update domain remap setting	2021-05-05 11:46:08 +00:00
nvidia	cbfs: Replace more instances of cbfs_boot_locate() with newer APIs	2021-03-17 08:10:20 +00:00
qualcomm	Coachz: Observe SPI_CLK voltage level is only 1.4V, need to adjust	2021-04-24 00:24:00 +00:00
rockchip	soc/rockchip/rk3399/sdram: Add channel to error message	2021-03-04 01:22:10 +00:00
samsung	commonlib/region: Turn addrspace_32bit into a more official API	2021-04-21 02:06:26 +00:00
sifive	memlayout: Store region sizes as separate symbols	2021-02-19 08:39:26 +00:00
ti	soc/ti/am335x/mmc.c: Fix memset length argument	2021-04-04 09:58:26 +00:00
ucb