Martin Roth f3314c20de soc/amd/cezanne: Clear eSPI ranges before configuring eSPI ... The Cezanne PSP configures the eSPI with the assumption that it's a majolica, setting up both the serial port and the majolica EC IO decode ranges. Since guybrush is NOT a majolica, this doesn't work very well there. Clearing the decode ranges allows the guybrush platform to set the decode ranges needed for its EC. BUG=b:183524609 TEST=Set up eSPI on Guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I77cfb948cb9ae6d1cf001bd9e66cede8d93f50b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/51749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>		2021-04-05 00:44:19 +00:00
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amd	soc/amd/cezanne: Clear eSPI ranges before configuring eSPI	2021-04-05 00:44:19 +00:00
cavium	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
example	arch/x86: Move prologue to .init section	2021-01-07 11:02:03 +00:00
intel	soc/intel/alderlake: Enable logging of wake sources for S0ix	2021-03-30 15:37:18 +00:00
mediatek	soc/mediatek: Adjust hsa, hbp, hfp packets for MIPI_DSI_MODE_LINE_END	2021-03-27 10:03:41 +00:00
nvidia	cbfs: Replace more instances of cbfs_boot_locate() with newer APIs	2021-03-17 08:10:20 +00:00
qualcomm	cbfs: Remove prog_locate() for payloads (SELF and FIT)	2021-03-17 00:13:53 +00:00
rockchip	soc/rockchip/rk3399/sdram: Add channel to error message	2021-03-04 01:22:10 +00:00
samsung	cbfs: Pull handling of the CBFS_CACHE mem_pool into CBFS core	2021-03-08 22:31:29 +00:00
sifive	memlayout: Store region sizes as separate symbols	2021-02-19 08:39:26 +00:00
ti	soc/ti/am335x/mmc.c: Fix memset length argument	2021-04-04 09:58:26 +00:00
ucb