coreboot-kgpe-d16/src/soc/intel/baytrail
Aaron Durbin f3f409bf55 baytrail: correct MMC pci location
The original documentation was incorrect. Fix the pci
device for the MMC port to reflect reality.

MMC is at 00:17.0 with a device id of 0x0f50.

BUG=None
BRANCH=None
TEST=Built.

Change-Id: Ic18665b7dda5f386e72d1a5255e4e57d5b631eb0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172772
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4884
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-16 20:37:22 +01:00
..
acpi
baytrail baytrail: correct MMC pci location 2014-02-16 20:37:22 +01:00
bootblock baytrail: load microcode in bootblock 2014-02-05 05:24:13 +01:00
microcode baytrail: add 316 microcode 2014-02-05 05:23:46 +01:00
romstage coreboot: infrastructure for different ramstage loaders 2014-02-15 18:39:29 +01:00
chip.c baytrail: introduce pattrs 2014-01-31 20:42:37 +01:00
chip.h
gpio.c rambi: Add ncore GPIO config tables 2014-02-11 22:21:20 +01:00
iosf.c baytrail: print dram configuration 2014-02-13 16:55:56 +01:00
Kconfig baytrail: add reset support 2014-02-11 22:22:25 +01:00
Makefile.inc baytrail: add reset support 2014-02-11 22:22:25 +01:00
memmap.c
mrc_cache.c
northcluster.c baytrail: set host memory map 2014-01-31 20:42:16 +01:00
nvm.c
placeholders.c
ramstage.c baytrail: allow downstream use of SSE instructions 2014-02-13 16:55:45 +01:00
reset.c baytrail: add reset support 2014-02-11 22:22:25 +01:00
spi.c
tsc_freq.c baytrail: fix tsc rate 2014-02-16 20:37:03 +01:00