Aaron Durbin f5ff854c36 soc/intel: indicate to build system that XIP_ROM_SIZE isn't used ... The XIP_ROM_SIZE Kconfig variable isn't used for these chipsets. Therefore, indicate as such so that romstage can be placed in cbfs less rigidly. Change-Id: If5cae10b90e05029df56c282e8adf37fa0102955 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14626 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>		2016-05-06 16:50:00 +02:00
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acpi	acpi/: add missing license header	2016-01-14 22:52:11 +01:00
arch	arch/x86: Drop CBFS_BASE_ADDRESS	2016-05-03 11:41:55 +02:00
commonlib	ensure correct byte ordering for cbfs segment list	2016-04-25 23:30:00 +02:00
console	arch/x86: introduce postcar stage/phase	2016-03-23 14:24:30 +01:00
cpu	cpu/x86: don't treat all chipsets the same regarding XIP_ROM_SIZE	2016-05-06 16:49:37 +02:00
device	payloads: add iPXE 'payload' build	2016-04-13 17:45:37 +02:00
drivers	drivers/xpowers: Switch to src/drivers/[X]/[Y]/ scheme	2016-05-04 22:14:44 +02:00
ec	kbuild: Allow drivers to fit src/drivers/[X]/[Y]/ scheme	2016-04-19 18:34:18 +02:00
include	cpu/x86/mp_init: reduce exposure of internal implementation	2016-05-06 16:47:54 +02:00
lib	lib/reg_script: Fix braces	2016-05-05 19:41:29 +02:00
mainboard	rdc/r8610: Move to src/soc	2016-05-05 20:08:58 +02:00
northbridge	rdc/r8610: Move to src/soc	2016-05-05 20:08:58 +02:00
soc	soc/intel: indicate to build system that XIP_ROM_SIZE isn't used	2016-05-06 16:50:00 +02:00
southbridge	rdc/r8610: Move to src/soc	2016-05-05 20:08:58 +02:00
superio	superio/smsc/mec1308: Fix AddressMax value for SMBX mailbox	2016-04-13 23:39:28 +02:00
vendorcode	vendorcode/intel/fsp/fsp1_1/quark: Update FspUpdVpd.h	2016-05-03 22:53:20 +02:00
Kconfig	lib/coreboot_table: use the architecture dependent table size	2016-05-02 20:03:34 +02:00