2024-07-24 17:00:17 +02:00
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\babel@toc {english}{}\relax
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2024-08-25 11:54:54 +02:00
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\contentsline {chapter}{Acknowledgments}{3}{chapter*.1}%
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\contentsline {chapter}{Abstract}{4}{chapter*.2}%
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\contentsline {chapter}{List of Figures}{7}{chapter*.2}%
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\contentsline {chapter}{List of Listings}{8}{chapter*.2}%
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\contentsline {chapter}{\numberline {1}Introduction to firmware and BIOS evolution}{9}{chapter.1}%
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\contentsline {section}{\numberline {1.1}Historical context of BIOS}{9}{section.1.1}%
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\contentsline {subsection}{\numberline {1.1.1}Definition and origin}{9}{subsection.1.1.1}%
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\contentsline {subsection}{\numberline {1.1.2}Functionalities and limitations}{10}{subsection.1.1.2}%
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\contentsline {section}{\numberline {1.2}Modern BIOS and UEFI}{11}{section.1.2}%
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\contentsline {subsection}{\numberline {1.2.1}Transition from traditional BIOS to UEFI (Unified Extensible Firmware Interface)}{11}{subsection.1.2.1}%
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\contentsline {subsection}{\numberline {1.2.2}An other way with \textit {coreboot}}{11}{subsection.1.2.2}%
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\contentsline {section}{\numberline {1.3}Shift in firmware responsibilities}{13}{section.1.3}%
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\contentsline {chapter}{\numberline {2}Characteristics of ASUS KGPE-D16 mainboard}{14}{chapter.2}%
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\contentsline {section}{\numberline {2.1}Overview of ASUS KGPE-D16 hardware}{15}{section.2.1}%
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\contentsline {section}{\numberline {2.2}Chipset}{16}{section.2.2}%
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\contentsline {section}{\numberline {2.3}Processors}{18}{section.2.3}%
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\contentsline {section}{\numberline {2.4}Baseboard Management Controller}{19}{section.2.4}%
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\contentsline {chapter}{\numberline {3}Key components in modern firmware}{21}{chapter.3}%
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\contentsline {section}{\numberline {3.1}General structure of coreboot}{21}{section.3.1}%
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2024-08-25 15:57:26 +02:00
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\contentsline {subsection}{\numberline {3.1.1}Bootblock}{22}{subsection.3.1.1}%
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2024-08-25 11:54:54 +02:00
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\contentsline {subsection}{\numberline {3.1.2}Romstage}{24}{subsection.3.1.2}%
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\contentsline {subsection}{\numberline {3.1.3}Ramstage}{25}{subsection.3.1.3}%
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\contentsline {subsubsection}{\numberline {3.1.3.1}Advanced Configuration and Power Interface}{25}{subsubsection.3.1.3.1}%
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\contentsline {subsubsection}{\numberline {3.1.3.2}System Management Mode}{26}{subsubsection.3.1.3.2}%
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\contentsline {subsection}{\numberline {3.1.4}Payload}{26}{subsection.3.1.4}%
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\contentsline {section}{\numberline {3.2}AMD Platform Security Processor and Intel Management Engine}{27}{section.3.2}%
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\contentsline {chapter}{\numberline {4}Memory initialization and training}{29}{chapter.4}%
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\contentsline {section}{\numberline {4.1}Importance of DDR3 Memory Initialization}{29}{section.4.1}%
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\contentsline {subsection}{\numberline {4.1.1}General steps for DDR3 configuration}{30}{subsection.4.1.1}%
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2024-08-25 15:57:26 +02:00
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\contentsline {section}{\numberline {4.2}Memory initialization techniques}{33}{section.4.2}%
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\contentsline {subsection}{\numberline {4.2.1}Memory training algorithms}{33}{subsection.4.2.1}%
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\contentsline {subsection}{\numberline {4.2.2}BIOS and Kernel Developer Guide (BKDG) recommendations}{34}{subsection.4.2.2}%
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\contentsline {subsubsection}{\numberline {4.2.2.1}DDR3 initialization procedure}{35}{subsubsection.4.2.2.1}%
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\contentsline {subsubsection}{\numberline {4.2.2.2}ZQ calibration process}{35}{subsubsection.4.2.2.2}%
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\contentsline {subsubsection}{\numberline {4.2.2.3}Write leveling process}{36}{subsubsection.4.2.2.3}%
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\contentsline {section}{\numberline {4.3}Current implementation and potential improvements}{37}{section.4.3}%
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\contentsline {subsection}{\numberline {4.3.1}Current implementation in coreboot on the KGPE-D16}{37}{subsection.4.3.1}%
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2024-08-25 18:51:20 +02:00
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\contentsline {subsubsection}{\numberline {4.3.1.1}Details on the DQS training function}{47}{subsubsection.4.3.1.1}%
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\contentsline {subsubsection}{\numberline {4.3.1.2}Details on the DQS receiver training function}{48}{subsubsection.4.3.1.2}%
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\contentsline {subsubsection}{\numberline {4.3.1.3}Details on the DQS position training function}{48}{subsubsection.4.3.1.3}%
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\contentsline {subsection}{\numberline {4.3.2}Potential enhancements [WIP]}{48}{subsection.4.3.2}%
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\contentsline {chapter}{\numberline {5}Virtualization of the operating system through firmware abstraction}{52}{chapter.5}%
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\contentsline {section}{\numberline {5.1}ACPI and abstraction of hardware control}{52}{section.5.1}%
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\contentsline {section}{\numberline {5.2}SMM as a hidden execution layer}{53}{section.5.2}%
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\contentsline {section}{\numberline {5.3}UEFI and persistence}{53}{section.5.3}%
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\contentsline {subsection}{\numberline {5.3.1}Memory Management}{54}{subsection.5.3.1}%
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\contentsline {subsection}{\numberline {5.3.2}File System Management}{54}{subsection.5.3.2}%
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\contentsline {subsection}{\numberline {5.3.3}Device Drivers}{54}{subsection.5.3.3}%
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\contentsline {subsection}{\numberline {5.3.4}Power Management}{54}{subsection.5.3.4}%
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\contentsline {section}{\numberline {5.4}Intel and AMD: control beyond the OS}{54}{section.5.4}%
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\contentsline {section}{\numberline {5.5}The OS as a virtualized environment}{55}{section.5.5}%
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\contentsline {chapter}{Conclusion}{56}{chapter*.4}%
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\contentsline {chapter}{Bibliography}{57}{chapter*.4}%
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\contentsline {chapter}{GNU Free Documentation License}{64}{chapter*.6}%
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