2019-03-25 23:10:06 +01:00
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//----------------------------------------------------------------------------//
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2019-04-22 20:15:32 +02:00
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// GNU GPL OS/K //
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// //
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// Desc: Interrupt related functions //
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// //
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// //
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// Copyright © 2018-2019 The OS/K Team //
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// //
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// This file is part of OS/K. //
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// //
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// OS/K is free software: you can redistribute it and/or modify //
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// it under the terms of the GNU General Public License as published by //
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// the Free Software Foundation, either version 3 of the License, or //
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// any later version. //
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// //
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// OS/K is distributed in the hope that it will be useful, //
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// but WITHOUT ANY WARRANTY//without even the implied warranty of //
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the //
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// GNU General Public License for more details. //
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// //
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// You should have received a copy of the GNU General Public License //
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// along with OS/K. If not, see <https://www.gnu.org/licenses/>. //
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2019-03-25 23:10:06 +01:00
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//----------------------------------------------------------------------------//
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2019-04-09 17:16:13 +02:00
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#include <kernel/base.h>
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2019-04-01 23:53:36 +02:00
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#include <kernel/cpu.h>
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2019-04-22 20:15:32 +02:00
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#include <kernel/boot.h>
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2019-04-22 22:32:21 +02:00
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#include <kernel/iomisc.h>
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2019-04-01 23:51:48 +02:00
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2019-04-22 20:15:32 +02:00
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IdtEntry_t idt[256] = { 0 };
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IdtPtr_t idtPtr;
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2019-03-25 23:10:06 +01:00
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2019-04-22 22:32:21 +02:00
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void CpuIdtSetup(void)
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2019-04-22 20:15:32 +02:00
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{
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2019-04-22 22:32:21 +02:00
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disablePIC();
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2019-04-01 23:51:48 +02:00
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2019-04-22 20:15:32 +02:00
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ushort codeSeg = (ushort)(ulong)BtLoaderInfo.codeSegment;
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// Set IDT ptr
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idtPtr.limit = (sizeof(IdtEntry_t) * 256) - 1;
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idtPtr.base = &idt;
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// Set IDT gates
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idtSet(0, (ulong)isr0, codeSeg, 0x8E);
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idtSet(1, (ulong)isr1, codeSeg, 0x8E);
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idtSet(2, (ulong)isr2, codeSeg, 0x8E);
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idtSet(3, (ulong)isr3, codeSeg, 0x8E);
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idtSet(4, (ulong)isr4, codeSeg, 0x8E);
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idtSet(5, (ulong)isr5, codeSeg, 0x8E);
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idtSet(6, (ulong)isr6, codeSeg, 0x8E);
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idtSet(7, (ulong)isr7, codeSeg, 0x8E);
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idtSet(8, (ulong)isr8, codeSeg, 0x8E);
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idtSet(9, (ulong)isr9, codeSeg, 0x8E);
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idtSet(10, (ulong)isr10, codeSeg, 0x8E);
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idtSet(11, (ulong)isr11, codeSeg, 0x8E);
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idtSet(12, (ulong)isr12, codeSeg, 0x8E);
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idtSet(13, (ulong)isr13, codeSeg, 0x8E);
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idtSet(14, (ulong)isr14, codeSeg, 0x8E);
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//idtSet(15, (ulong)isr15, codeSeg, 0x8E); INTEL RESERVED
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idtSet(16, (ulong)isr16, codeSeg, 0x8E);
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idtSet(17, (ulong)isr17, codeSeg, 0x8E);
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idtSet(18, (ulong)isr18, codeSeg, 0x8E);
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idtSet(19, (ulong)isr19, codeSeg, 0x8E);
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idtSet(20, (ulong)isr20, codeSeg, 0x8E);
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//idtSet(21, (ulong)isr21, codeSeg, 0x8E); INTEL RESERVED
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//idtSet(22, (ulong)isr22, codeSeg, 0x8E); INTEL RESERVED
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//idtSet(23, (ulong)isr23, codeSeg, 0x8E); INTEL RESERVED
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//idtSet(24, (ulong)isr24, codeSeg, 0x8E); INTEL RESERVED
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//idtSet(25, (ulong)isr25, codeSeg, 0x8E); INTEL RESERVED
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//idtSet(26, (ulong)isr26, codeSeg, 0x8E); INTEL RESERVED
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//idtSet(27, (ulong)isr27, codeSeg, 0x8E); INTEL RESERVED
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//idtSet(28, (ulong)isr28, codeSeg, 0x8E); INTEL RESERVED
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//idtSet(29, (ulong)isr29, codeSeg, 0x8E); INTEL RESERVED
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//idtSet(30, (ulong)isr30, codeSeg, 0x8E); INTEL RESERVED
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// Load IDT
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2019-04-22 22:32:21 +02:00
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DebugLog("[IdtSetup] Filled \n");
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2019-04-22 20:15:32 +02:00
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idtInit();
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2019-04-22 22:32:21 +02:00
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DebugLog("[IdtSetup] Initialized !\n");
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2019-03-25 23:10:06 +01:00
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}
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2019-04-22 17:19:53 +02:00
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2019-04-22 20:15:32 +02:00
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void idtSet(uchar rank, ulong base, ushort selector, uchar flags)
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{
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// Set Base Address
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idt[rank].baseLow = base & 0xFFFF;
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idt[rank].baseMid = (base >> 16) & 0xFFFF;
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idt[rank].baseHigh = (base >> 32) & 0xFFFFFFFF;
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// Set Selector
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idt[rank].selector = selector;
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idt[rank].flags = flags;
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// Set Reserved Areas to Zero
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idt[rank].reservedIst = 0;
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idt[rank].reserved = 0;
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}
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2019-04-22 22:32:21 +02:00
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void disablePIC(void) {
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// Set ICW1
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IoWriteByteOnPort(0x20, 0x11);
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IoWriteByteOnPort(0xa0, 0x11);
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// Set ICW2 (IRQ base offsets)
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IoWriteByteOnPort(0x21, 0xe0);
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IoWriteByteOnPort(0xa1, 0xe8);
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// Set ICW3
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IoWriteByteOnPort(0x21, 4);
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IoWriteByteOnPort(0xa1, 2);
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// Set ICW4
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IoWriteByteOnPort(0x21, 1);
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IoWriteByteOnPort(0xa1, 1);
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// Set OCW1 (interrupt masks)
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IoWriteByteOnPort(0x21, 0xff);
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IoWriteByteOnPort(0xa1, 0xff);
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// ENABLING LOCAL APIC
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uint *val = (void*)0xfee000f0;
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*val |= (1<<8);
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}
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void isrHandler(Registers_t regs)
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{
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DebugLog("Interrupt %d !!! \n", regs.intNo);
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return;
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}
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