2013-10-04 23:00:07 +02:00
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <types.h>
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#include <string.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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2017-06-25 05:53:37 +02:00
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#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
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2013-10-04 23:00:07 +02:00
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#include <x86emu/x86emu.h>
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#endif
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#include <pc80/mc146818rtc.h>
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#include <arch/acpi.h>
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#include <arch/io.h>
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#include <arch/interrupt.h>
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#include <boot/coreboot_tables.h>
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2013-11-09 02:23:26 +01:00
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#include <smbios.h>
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2013-10-28 17:24:53 +01:00
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#include "ec.h"
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2017-01-12 19:19:21 +01:00
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#include <variant/onboard.h>
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2014-10-08 01:42:17 +02:00
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#include <soc/gpio.h>
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2014-05-02 05:20:06 +02:00
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#include <bootstate.h>
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2016-07-26 04:31:41 +02:00
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#include <vendorcode/google/chromeos/chromeos.h>
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2013-10-04 23:00:07 +02:00
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void mainboard_suspend_resume(void)
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{
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}
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2017-06-25 05:53:37 +02:00
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#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
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2013-10-04 23:00:07 +02:00
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static int int15_handler(void)
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{
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int res = 1;
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printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
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__func__, X86_AX, X86_BX, X86_CX, X86_DX);
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switch (X86_AX) {
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case 0x5f34:
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/*
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* Set Panel Fitting Hook:
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* bit 2 = Graphics Stretching
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* bit 1 = Text Stretching
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* bit 0 = Centering (do not set with bit1 or bit2)
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* 0 = video bios default
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*/
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X86_AX = 0x005f;
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X86_CX = 0x0001;
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res = 1;
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break;
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case 0x5f35:
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/*
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* Boot Display Device Hook:
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* bit 0 = CRT
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2014-04-01 19:13:38 +02:00
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* bit 1 = TV
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* bit 2 = EFP (HDMI)
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* bit 3 = LFP (eDP)*
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2013-10-04 23:00:07 +02:00
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* bit 4 = CRT2
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2014-04-01 19:13:38 +02:00
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* bit 5 = TV2
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2014-02-22 21:26:55 +01:00
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* bit 6 = EFP2
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2013-10-04 23:00:07 +02:00
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* bit 7 = LFP2
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*/
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X86_AX = 0x005f;
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2014-04-01 19:13:38 +02:00
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X86_CX = 0x0008;
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2013-10-04 23:00:07 +02:00
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res = 1;
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break;
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case 0x5f51:
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/*
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* Hook to select active LFP configuration:
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* 00h = No LVDS, VBIOS does not enable LVDS
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* 01h = Int-LVDS, LFP driven by integrated LVDS decoder
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* 02h = SVDO-LVDS, LFP driven by SVDO decoder
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* 03h = eDP, LFP Driven by Int-DisplayPort encoder
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*/
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X86_AX = 0x005f;
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X86_CX = 0x0003;
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res = 1;
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break;
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case 0x5f70:
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switch ((X86_CX >> 8) & 0xff) {
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case 0:
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/* Get Mux */
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X86_AX = 0x005f;
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X86_CX = 0x0000;
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res = 1;
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break;
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case 1:
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/* Set Mux */
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X86_AX = 0x005f;
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X86_CX = 0x0000;
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res = 1;
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break;
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case 2:
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/* Get SG/Non-SG mode */
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X86_AX = 0x005f;
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X86_CX = 0x0000;
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res = 1;
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break;
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default:
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/* Interrupt was not handled */
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printk(BIOS_DEBUG,
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"Unknown INT15 5f70 function: 0x%02x\n",
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((X86_CX >> 8) & 0xff));
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break;
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}
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break;
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2013-11-09 02:23:26 +01:00
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default:
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2013-10-04 23:00:07 +02:00
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printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
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break;
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}
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return res;
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}
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#endif
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2013-10-28 17:24:53 +01:00
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static void mainboard_init(device_t dev)
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{
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mainboard_ec_init();
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Add Baytrail ChromeOS devices using variant scheme
Add new ChromeOS devices banjo, candy, clapper, glimmer, gnawty,
heli, kip, orco, quawks, squawks, sumo, swanky, and winky using
their common reference board (rambi) as a base.
Chromium sources used:
firmware-banjo-5216.334.B 32ec493 [chromeos: vboot_loader: Set...]
firmware-candy-5216.310.B 519ff11 [baytrail: Preserve VbNv around...]
firmware-clapper-5216.199.B 80d55e3 [baytrail: add code for...]
firmware-glimmer-5216.198.B fae0770 [baytrail: add code for...]
firmware-gnawty-5216.239.B 952adb7 [Gnawty/Olay: Add 2nd source...]
firmware-heli-5216.392.B f1f3604 [helis: Lock ME / TXE section...]
firmware-kip-5216.227.B db3c5d9 [kip: update spd for for MT41K256M16*]
firmware-orco-5216.362.B 76f1651 [Orco: Adjust rx delay for norm.]
firmware-quawks-5216.204.B edb60c9 [Quawks: Update SPD data]
firmware-squawks-5216.152.B c6573dc [Squawks: Update SPD data]
firmware-sumo-5216.382.B c62b6f23 [Ninja, Sumo: Add SPD source...]
firmware-swanky-5216.238.B 233b2a7 [Swanky: update SPD table]
firmware-winky-5216.265.B ce91ffc [Add to support HT Micron...]
The same basic cleanup/changes are made here as with the initial BYT
variant commit:
- remove unused ACPI trackpad/touchscreen devices
- correct I2C addresses in SMBIOS entries
- clean up comment formatting
- remove ACPI device for unused light sensor
- switch I2C ACPI devices from edge to level triggered interrupts,
for better compatibility/functionality (and to be consistent
with other recently-upstreamed ChromeOS devices)
- Micron 2GB SPD file for kip with updated values renamed to distinguish
from same file used by other boards
Change-Id: Ic66f9b539afb5aff32c4c1a8563f6612f5a2927c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18164
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-17 00:32:38 +01:00
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#if IS_ENABLED(CONFIG_BOARD_GOOGLE_NINJA) || IS_ENABLED(CONFIG_BOARD_GOOGLE_SUMO)
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2017-01-12 19:19:21 +01:00
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lan_init();
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#endif
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2013-10-28 17:24:53 +01:00
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}
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2013-11-09 02:23:26 +01:00
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static int mainboard_smbios_data(device_t dev, int *handle,
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unsigned long *current)
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{
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int len = 0;
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2017-01-12 19:19:21 +01:00
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#ifdef BOARD_TRACKPAD_NAME
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2013-11-09 02:23:26 +01:00
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len += smbios_write_type41(
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current, handle,
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BOARD_TRACKPAD_NAME, /* name */
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BOARD_TRACKPAD_IRQ, /* instance */
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BOARD_TRACKPAD_I2C_BUS, /* segment */
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BOARD_TRACKPAD_I2C_ADDR, /* bus */
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0, /* device */
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0); /* function */
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2017-01-12 19:19:21 +01:00
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#endif
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#ifdef BOARD_TOUCHSCREEN_NAME
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2013-11-09 02:23:26 +01:00
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len += smbios_write_type41(
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current, handle,
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BOARD_TOUCHSCREEN_NAME, /* name */
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BOARD_TOUCHSCREEN_IRQ, /* instance */
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BOARD_TOUCHSCREEN_I2C_BUS, /* segment */
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BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */
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0, /* device */
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0); /* function */
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2017-01-12 19:19:21 +01:00
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#endif
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2013-11-09 02:23:26 +01:00
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return len;
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}
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2013-10-04 23:00:07 +02:00
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// mainboard_enable is executed as first thing after
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// enumerate_buses().
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static void mainboard_enable(device_t dev)
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{
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2013-10-28 17:24:53 +01:00
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dev->ops->init = mainboard_init;
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2013-11-09 02:23:26 +01:00
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dev->ops->get_smbios_data = mainboard_smbios_data;
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2016-07-26 04:31:41 +02:00
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dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
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2017-06-25 05:53:37 +02:00
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#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
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2013-10-04 23:00:07 +02:00
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/* Install custom int15 handler for VGA OPROM */
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mainboard_interrupt_handlers(0x15, &int15_handler);
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#endif
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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2014-05-02 05:20:06 +02:00
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static void edp_vdden_cb(void *unused)
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{
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ncore_select_func(SOC_DDI1_VDDEN_PAD, PAD_FUNC2);
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}
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2015-03-16 23:30:09 +01:00
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BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL);
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