2006-01-28 00:46:30 +01:00
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#include <cpu/amd/gx2def.h>
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2006-02-23 22:39:19 +01:00
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static void sdram_set_registers(const struct mem_controller *ctrl)
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2006-01-28 00:46:30 +01:00
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{
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}
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2006-02-23 22:39:19 +01:00
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/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
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* Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
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static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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2006-01-28 00:46:30 +01:00
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{
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2006-02-23 22:39:19 +01:00
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int i;
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msr_t msr;
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2006-03-02 22:33:01 +01:00
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/* 2. clock gating for PMode */
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2006-02-23 22:39:19 +01:00
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msr = rdmsr(0x20002004);
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2006-03-02 22:33:01 +01:00
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msr.lo &= ~0x04;
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msr.lo |= 0x01;
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2006-02-23 22:39:19 +01:00
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wrmsr(0x20002004, msr);
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/* undocmented bits in GX, in LX there are
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* 8 bits in PM1_UP_DLY */
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msr = rdmsr(0x2000001a);
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msr.lo = 0x0101;
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wrmsr(0x2000001a, msr);
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2010-03-31 16:47:43 +02:00
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//print_debug("sdram_enable step 2\n");
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2006-02-23 22:39:19 +01:00
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/* 3. release CKE mask to enable CKE */
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msr = rdmsr(0x2000001d);
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2006-03-02 22:33:01 +01:00
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msr.lo &= ~(0x03 << 8);
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2006-02-23 22:39:19 +01:00
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wrmsr(0x2000201d, msr);
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2010-03-31 16:47:43 +02:00
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//print_debug("sdram_enable step 3\n");
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2006-02-23 22:39:19 +01:00
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2006-03-02 22:33:01 +01:00
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/* 4. set and clear REF_TST 16 times, more shouldn't hurt
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* why this is before EMRS and MRS ? */
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2006-03-01 00:07:27 +01:00
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for (i = 0; i < 19; i++) {
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msr = rdmsr(0x20000018);
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msr.lo |= (0x01 << 3);
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wrmsr(0x20000018, msr);
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2006-03-02 22:33:01 +01:00
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msr.lo &= ~(0x01 << 3);
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2006-03-01 00:07:27 +01:00
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wrmsr(0x20000018, msr);
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}
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2010-03-31 16:47:43 +02:00
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//print_debug("sdram_enable step 4\n");
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2006-02-23 22:39:19 +01:00
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/* 5. set refresh interval */
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msr = rdmsr(0x20000018);
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2006-03-02 22:33:01 +01:00
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msr.lo &= ~(0xffff << 8);
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msr.lo |= (0x34 << 8);
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2006-02-23 22:39:19 +01:00
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wrmsr(0x20000018, msr);
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/* set refresh staggering to 4 SDRAM clocks */
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msr = rdmsr(0x20000018);
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2006-03-02 22:33:01 +01:00
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msr.lo &= ~(0x03 << 6);
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msr.lo |= (0x00 << 6);
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2006-02-23 22:39:19 +01:00
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wrmsr(0x20000018, msr);
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2010-03-31 16:47:43 +02:00
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//print_debug("sdram_enable step 5\n");
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2006-02-23 22:39:19 +01:00
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2006-03-02 22:33:01 +01:00
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/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
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2006-02-23 22:39:19 +01:00
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msr = rdmsr(0x20000018);
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msr.lo |= ((0x01 << 28) | 0x01);
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wrmsr(0x20000018, msr);
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2006-03-02 22:33:01 +01:00
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msr.lo &= ~((0x01 << 28) | 0x01);
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2006-02-23 22:39:19 +01:00
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wrmsr(0x20000018, msr);
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2010-03-31 16:47:43 +02:00
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//print_debug("sdram_enable step 6\n");
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2006-02-23 22:39:19 +01:00
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/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
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* it is documented in LX datasheet */
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/* load Mode Register by set and clear PROG_DRAM */
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msr = rdmsr(0x20000018);
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msr.lo |= ((0x01 << 27) | 0x01);
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wrmsr(0x20000018, msr);
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2006-03-02 22:33:01 +01:00
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msr.lo &= ~((0x01 << 27) | 0x01);
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2006-02-23 22:39:19 +01:00
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wrmsr(0x20000018, msr);
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2010-03-31 16:47:43 +02:00
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//print_debug("sdram_enable step 7\n");
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2006-02-23 22:39:19 +01:00
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/* 8. load Mode Register by set and clear PROG_DRAM */
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msr = rdmsr(0x20000018);
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msr.lo |= 0x01;
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wrmsr(0x20000018, msr);
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2006-03-02 22:33:01 +01:00
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msr.lo &= ~0x01;
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2006-02-23 22:39:19 +01:00
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wrmsr(0x20000018, msr);
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2010-03-31 16:47:43 +02:00
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//print_debug("sdram_enable step 8\n");
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2006-02-28 16:39:25 +01:00
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2006-02-23 22:39:19 +01:00
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/* wait 200 SDCLKs */
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for (i = 0; i < 200; i++)
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outb(0xaa, 0x80);
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/* load RDSYNC */
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2006-02-28 16:39:25 +01:00
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msr = rdmsr(0x2000001f);
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2006-03-13 22:58:43 +01:00
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msr.hi = 0x000ff310;
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2006-09-18 06:23:23 +02:00
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/* the above setting is supposed to be good for "slow" ram. We have found that for
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* some dram, at some clock rates, e.g. hynix at 366/244, this will actually
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* cause errors. The fix is to just set it to 0x310. Tested on 3 boards
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* with 3 different type of dram -- Hynix, PSC, infineon.
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* I am leaving this comment here so that at some future time nobody is tempted
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* to mess with this setting -- RGM, 9/2006
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*/
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msr.hi = 0x00000310;
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2006-03-01 00:07:27 +01:00
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msr.lo = 0x00000000;
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2006-02-28 16:39:25 +01:00
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wrmsr(0x2000001f, msr);
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2006-02-23 22:39:19 +01:00
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2006-03-01 00:07:27 +01:00
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/* set delay control */
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msr = rdmsr(0x4c00000f);
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2006-03-02 22:33:01 +01:00
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msr.hi = 0x830d415a;
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msr.lo = 0x8ea0ad6a;
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2006-03-01 00:07:27 +01:00
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wrmsr(0x4c00000f, msr);
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2006-09-13 03:57:47 +02:00
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/* Fixes from Jordan Crouse of AMD. */
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/* make sure there is nothing stale in the cache */
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__asm__("wbinvd\n");
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2010-03-31 16:47:43 +02:00
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print_debug("RAM DLL lock\n");
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2006-09-13 03:57:47 +02:00
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/* The RAM dll needs a write to lock on so generate a few dummy writes */
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volatile unsigned long *ptr;
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for (i=0;i<5;i++) {
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ptr = (void *)i;
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*ptr = (unsigned long)i;
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}
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2006-05-02 05:07:11 +02:00
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2006-01-28 00:46:30 +01:00
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}
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