2014-01-12 15:26:15 +01:00
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chip northbridge/intel/sandybridge
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# Enable DisplayPort Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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# Enable Panel as LVDS and configure power delays
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register "gpu_panel_port_select" = "0" # LVDS
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register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
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register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
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register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
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register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
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2014-08-30 00:35:39 +02:00
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register "gfx.use_spread_spectrum_clock" = "1"
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register "gfx.lvds_dual_channel" = "0"
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register "gfx.link_frequency_270_mhz" = "1"
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register "gfx.lvds_num_lanes" = "1"
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2014-02-23 00:10:35 +01:00
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register "gpu_cpu_backlight" = "0x1155"
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register "gpu_pch_backlight" = "0x11551155"
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2014-01-12 15:26:15 +01:00
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device cpu_cluster 0 on
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chip cpu/intel/socket_rPGA989
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device lapic 0 on end
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end
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chip cpu/intel/model_206ax
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# Magic APIC ID to locate this chip
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device lapic 0xACAC off end
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# Coordinate with HW_ALL
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register "pstate_coord_type" = "0xfe"
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register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
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register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
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register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
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register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
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register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
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end
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end
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device domain 0 on
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2014-08-24 22:38:56 +02:00
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device pci 00.0 on
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subsystemid 0x17aa 0x21fa
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end # host bridge
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2014-01-12 15:26:15 +01:00
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device pci 01.0 off end # PCIe Bridge for discrete graphics
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2014-08-24 22:38:56 +02:00
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device pci 02.0 on
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subsystemid 0x17aa 0x21fa
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end # vga controller
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2014-01-12 15:26:15 +01:00
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "alt_gp_smi_en" = "0x0000"
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register "gpi1_routing" = "2"
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register "gpi8_routing" = "2"
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2014-01-24 14:38:10 +01:00
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# Enable SATA ports 0 (HDD bay) & 1 (dock) & 2 (msata)
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register "sata_port_map" = "0x7"
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2014-01-12 15:26:15 +01:00
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# Set max SATA speed to 6.0 Gb/s
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register "sata_interface_speed_support" = "0x3"
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register "gen1_dec" = "0x7c1601"
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register "gen2_dec" = "0x0c15e1"
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register "gen4_dec" = "0x0c06a1"
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2014-10-28 23:43:20 +01:00
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register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
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2015-01-31 17:46:29 +01:00
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register "xhci_switchable_ports" = "0xf"
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register "superspeed_capable_ports" = "0xf"
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2014-01-12 15:26:15 +01:00
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# Enable zero-based linear PCIe root port functions
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register "pcie_port_coalesce" = "1"
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2014-10-25 15:20:55 +02:00
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register "c2_latency" = "101" # c2 not supported
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register "p_cnt_throttling_supported" = "1"
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2014-01-12 15:26:15 +01:00
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2014-08-24 22:38:56 +02:00
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device pci 14.0 on
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subsystemid 0x17aa 0x21fa
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end # USB 3.0 Controller
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device pci 16.0 on
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subsystemid 0x17aa 0x21fa
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end # Management Engine Interface 1
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2014-01-12 15:26:15 +01:00
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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2014-08-24 22:38:56 +02:00
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device pci 19.0 on
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subsystemid 0x17aa 0x21f3
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end # Intel Gigabit Ethernet
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device pci 1a.0 on
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subsystemid 0x17aa 0x21fa
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end # USB2 EHCI #2
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device pci 1b.0 on
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subsystemid 0x17aa 0x21fa
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end # High Definition Audio
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device pci 1c.0 on
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subsystemid 0x17aa 0x21fa
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2014-10-27 02:45:22 +01:00
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chip drivers/ricoh/rce822
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register "sdwppol" = "1"
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register "disable_mask" = "0x87"
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device pci 00.0 on
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subsystemid 0x17aa 0x21fa
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end
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2014-08-24 22:38:56 +02:00
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end
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end # PCIe Port #1
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device pci 1c.1 on
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subsystemid 0x17aa 0x21fa
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end # PCIe Port #2
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device pci 1c.2 on
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subsystemid 0x17aa 0x21fa
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end # PCIe Port #3 (expresscard)
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2014-01-12 15:26:15 +01:00
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device pci 1c.3 off end # PCIe Port #4
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 off end # PCIe Port #7
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device pci 1c.7 off end # PCIe Port #8
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2014-08-24 22:38:56 +02:00
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device pci 1d.0 on
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subsystemid 0x17aa 0x21fa
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end # USB2 EHCI #1
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2014-01-12 15:26:15 +01:00
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on #LPC bridge
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2014-08-24 22:38:56 +02:00
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subsystemid 0x17aa 0x21fa
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2014-01-12 15:26:15 +01:00
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chip ec/lenovo/pmh7
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device pnp ff.1 on # dummy
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end
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register "backlight_enable" = "0x01"
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register "dock_event_enable" = "0x01"
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end
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chip ec/lenovo/h8
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device pnp ff.2 on # dummy
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io 0x60 = 0x62
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io 0x62 = 0x66
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io 0x64 = 0x1600
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io 0x66 = 0x1604
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end
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register "config0" = "0xa6"
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register "config1" = "0x09"
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register "config2" = "0xa0"
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register "config3" = "0xe0"
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register "has_keyboard_backlight" = "1"
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register "beepmask0" = "0x00"
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register "beepmask1" = "0x86"
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register "has_power_management_beeps" = "0"
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register "event2_enable" = "0xff"
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register "event3_enable" = "0xff"
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register "event4_enable" = "0xd0"
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register "event5_enable" = "0xfc"
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register "event6_enable" = "0x00"
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register "event7_enable" = "0x01"
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register "event8_enable" = "0x7b"
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register "event9_enable" = "0xff"
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register "eventa_enable" = "0x01"
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register "eventb_enable" = "0x00"
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register "eventc_enable" = "0xff"
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register "eventd_enable" = "0xff"
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register "evente_enable" = "0x0d"
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end
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end # LPC bridge
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2014-08-24 22:38:56 +02:00
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device pci 1f.2 on
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subsystemid 0x17aa 0x21fa
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end # SATA Controller 1
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2014-01-23 09:06:08 +01:00
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device pci 1f.3 on
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2014-08-24 22:38:56 +02:00
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subsystemid 0x17aa 0x21fa
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2014-01-23 09:06:08 +01:00
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# eeprom, 8 virtual devices, same chip
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chip drivers/i2c/at24rf08c
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device i2c 54 on end
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device i2c 55 on end
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device i2c 56 on end
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device i2c 57 on end
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device i2c 5c on end
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device i2c 5d on end
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device i2c 5e on end
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device i2c 5f on end
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end
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end # SMBus
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2014-01-12 15:26:15 +01:00
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device pci 1f.5 off end # SATA Controller 2
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2014-08-24 22:38:56 +02:00
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device pci 1f.6 on
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subsystemid 0x17aa 0x21fa
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end # Thermal
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2014-01-12 15:26:15 +01:00
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end
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end
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end
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