GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
coreboot-kgpe-d16/src/device/Kconfig

577 lines
16 KiB
Plaintext
Raw Normal View History

Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
##
## This file is part of the coreboot project.
##
YABEL update - drop x86emu + old biosemu in favor of YABEL - Add YABEL_DIRECTHW to get the old biosemu behavior - add support for vesa console using YABEL - add coreboot table entry with console information - add bootsplash support (reads /bootsplash.jpg from CBFS) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Pattrick Hueper <phueper@hueper.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 05:33:13 +01:00
## Copyright (C) 2007-2010 coresystems GmbH
Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
Various license header consistency fixes (trivial). - Consistently use the same wording and formatting for all license headers. - Remove useless whitespace, add missing whitespace, fix indentation. - Add missing "This file is part of the coreboot project." where needed. - Change "(C) Copyright John Doe" to "Copyright (C) John Doe" for consistency. - Add some missing "(C)" strings and copyright years where needed. - Move random comments and file descriptions out of the license header. - Drop incorrect file descriptions completely (e.g. lpc47m10x/Makefile.inc). There should be no changes in _content_ of the license headers, if you spot such changes that's a bug, please report! Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-16 00:10:19 +01:00
## the Free Software Foundation; version 2 of the License.
Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
GPLv2 notice: Unify all files to just use one space in »MA 02110-1301« In the file `COPYING` in the coreboot repository and upstream [1] just one space is used. The following command was used to convert all files. $ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/' [1] http://www.gnu.org/licenses/gpl-2.0.txt Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/2490 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-23 18:37:27 +01:00
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
##
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
menu "Devices"
Google Link: Add remaining code to support native graphics The Link native graphics commit 49428d84 [1] Add support for Google's Chromebook Pixel was missing some of the higher level bits, and hence could not be used. This is not new code -- it has been working since last August -- so the effort now is to get it into the tree and structure it in a way compatible with upstream coreboot. 1. Add options to src/device/Kconfig to enable native graphics. 2. Export the MTRR function for setting variable MTRRs. 3. Clean up some of the comments and white space. While I realize that the product name is Pixel, the mainboard in the coreboot tree is called Link, and that name is what we will use in our commits. [1] http://review.coreboot.org/2482 Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2531 Tested-by: build bot (Jenkins)
2013-02-26 19:07:40 +01:00
# Only set this in the mainboard
config MAINBOARD_HAS_NATIVE_VGA_INIT
bool
default n
drivers/xgi/z9s: Port Linux framebuffer initialization to coreboot Add native XGI Z9s framebuffer support to coreboot XGI initialization code largely taken from Linux 3.18.5 TEST: Booted KFSN4-DRE with XGI Volari Z9s into SeaBIOS with SeaVGABIOS enabled. Text appeared correctly on screen and interaction with graphical comboot menu was successful. However, Linux cleared the framebuffer on boot, rendering the screen useless until Linux loaded its native xgifb driver. Change-Id: I606a3892849fc578b0c4d74536aec0a0adef3be3 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/8331 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-02-03 01:25:34 +01:00
# FIXME Ugly hack to allow Z9s driver native framebuffer configuration
config NATIVE_VGA_INIT_USE_EDID
bool
default n if DRIVERS_XGI_Z9S
default y if !DRIVERS_XGI_Z9S
devices: Allow to configure textmode in native gfx init. Usefull to select between text mode which offers best compatibility with payloads and gfx mode which makes the best-looking screen. Also right now we have an unfortunate situation when qemu is in gfx mode while most real systems use text mode. Change-Id: Ifad7ba197875edfdd06eb932afeb5800229ef055 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5282 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-22 10:34:47 +01:00
config MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
bool
default n
Google Link: Add remaining code to support native graphics The Link native graphics commit 49428d84 [1] Add support for Google's Chromebook Pixel was missing some of the higher level bits, and hence could not be used. This is not new code -- it has been working since last August -- so the effort now is to get it into the tree and structure it in a way compatible with upstream coreboot. 1. Add options to src/device/Kconfig to enable native graphics. 2. Export the MTRR function for setting variable MTRRs. 3. Clean up some of the comments and white space. While I realize that the product name is Pixel, the mainboard in the coreboot tree is called Link, and that name is what we will use in our commits. [1] http://review.coreboot.org/2482 Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2531 Tested-by: build bot (Jenkins)
2013-02-26 19:07:40 +01:00
config MAINBOARD_DO_NATIVE_VGA_INIT
bool "Use native graphics initialization"
depends on MAINBOARD_HAS_NATIVE_VGA_INIT
default n
help
Some mainboards, such as the Google Link, allow initializing the display
without the need of a binary only VGA OPROM. Enabling this option may be
device/Kconfig: Add third person singular s to lacks Change-Id: I74be0dbbf8d99f58ac28bfac281ccd27d1500078 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4608 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-03 09:45:57 +01:00
faster, but also lacks flexibility in setting modes.
Google Link: Add remaining code to support native graphics The Link native graphics commit 49428d84 [1] Add support for Google's Chromebook Pixel was missing some of the higher level bits, and hence could not be used. This is not new code -- it has been working since last August -- so the effort now is to get it into the tree and structure it in a way compatible with upstream coreboot. 1. Add options to src/device/Kconfig to enable native graphics. 2. Export the MTRR function for setting variable MTRRs. 3. Clean up some of the comments and white space. While I realize that the product name is Pixel, the mainboard in the coreboot tree is called Link, and that name is what we will use in our commits. [1] http://review.coreboot.org/2482 Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2531 Tested-by: build bot (Jenkins)
2013-02-26 19:07:40 +01:00
If unsure, say N.
Various Kconfig fixes and improvements: - Add helps texts to multiple user-visible Kconfig options. - Improve some menu and option names. - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down (instead of up) when changing "no payload" to "ELF payload" (more intuitive, IMHO). - s/cbfs/cbfstool/. - Add some TODO items where needed. - Put GDB_STUB in a "Debugging" menu, no options should be top-level. There'll be more debug options later, I'm pretty sure. - Start converting help texts which are not user-visible to #-comments. - Re-order some options for more intuitive menus. - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them. - "Maximum reboot count" should proabably not be user-selectable, or at most if CONFIG_EXPERT (yet to be added) is enabled. It does definately not need its own "Misc options" menu. - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to run option ROMs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:15:40 +02:00
# TODO: Explain differences (if any) for onboard cards.
Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
config VGA_ROM_RUN
Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-10-07 01:47:51 +02:00
bool "Run VGA Option ROMs"
Run option ROMs in coreboot by default only if the payload is not SeaBIOS Change-Id: I29fb86ff3a3187b720ce5ef246c4eeee696ab5cd Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/1637 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-27 14:17:04 +02:00
default n if PAYLOAD_SEABIOS
default y if !PAYLOAD_SEABIOS
Google Link: Add remaining code to support native graphics The Link native graphics commit 49428d84 [1] Add support for Google's Chromebook Pixel was missing some of the higher level bits, and hence could not be used. This is not new code -- it has been working since last August -- so the effort now is to get it into the tree and structure it in a way compatible with upstream coreboot. 1. Add options to src/device/Kconfig to enable native graphics. 2. Export the MTRR function for setting variable MTRRs. 3. Clean up some of the comments and white space. While I realize that the product name is Pixel, the mainboard in the coreboot tree is called Link, and that name is what we will use in our commits. [1] http://review.coreboot.org/2482 Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2531 Tested-by: build bot (Jenkins)
2013-02-26 19:07:40 +01:00
depends on PCI && !PAYLOAD_SEABIOS && !MAINBOARD_DO_NATIVE_VGA_INIT || EXPERT
Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
help
Clarify that _ROM_RUN Kconfig options control if ROMs are run by coreboot Also clarify that enabling these options is generally not desirable if using SeaBIOS as payload since the option ROMs are run by SeaBIOS with more complete BIOS interrupt services available than coreboot. Change-Id: Ic4a45c351a4933aedad08d70a088eab04ca35b05 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/1636 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-27 13:45:51 +02:00
Execute VGA Option ROMs in coreboot if found. This is required
to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
payload.
When using a SeaBIOS payload it runs all option ROMs with much
more complete BIOS interrupt services available than coreboot,
which some option ROMs require in order to function correctly.
If unsure, say N when using SeaBIOS as payload, Y otherwise.
Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> tested on abuild only. Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-12 17:00:51 +02:00
Don't run VGA option ROMs on S3 resume. This will save us a few 100 ms on resume. Change-Id: Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/715 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-23 19:33:58 +02:00
config S3_VGA_ROM_RUN
Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-10-07 01:47:51 +02:00
bool "Re-run VGA Option ROMs on S3 resume"
Don't run VGA option ROMs on S3 resume. This will save us a few 100 ms on resume. Change-Id: Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/715 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-23 19:33:58 +02:00
default y
depends on VGA_ROM_RUN && HAVE_ACPI_RESUME
help
Clarify that _ROM_RUN Kconfig options control if ROMs are run by coreboot Also clarify that enabling these options is generally not desirable if using SeaBIOS as payload since the option ROMs are run by SeaBIOS with more complete BIOS interrupt services available than coreboot. Change-Id: Ic4a45c351a4933aedad08d70a088eab04ca35b05 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/1636 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-27 13:45:51 +02:00
Execute VGA Option ROMs in coreboot when resuming from S3 suspend.
When using a SeaBIOS payload it runs all option ROMs with much
more complete BIOS interrupt services available than coreboot,
which some option ROMs require in order to function correctly.
If unsure, say N when using SeaBIOS as payload, Y otherwise.
Don't run VGA option ROMs on S3 resume. This will save us a few 100 ms on resume. Change-Id: Iabf4c8ab88662ba41236162f0a6f5bd80d8c1255 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/715 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-09-23 19:33:58 +02:00
device: provide option to always load PCI option roms Certain kernel drivers require the presence of option rom contents because the board's static configuration information is located within the blob. Therefore, allow a chipset/board to instruct the pci device handling code to always load but not necessarily run the option rom. BUG=chrome-os-partner:25885 BRANCH=baytrail TEST=Both enabling and not enabling this option shows expected behavior. Change-Id: Ib0f65ffaf1a861b543573a062c291f4ba491ffe0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188720 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5594 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-05-01 15:31:34 +02:00
config ALWAYS_LOAD_OPROM
def_bool n
depends on VGA_ROM_RUN
help
src/.../Kconfig: various small fixes to texts Fixed spelling and added empty lines to separate the help from the text automatically added during make menuconfig. Change-Id: I6eee2c86e30573deb8cf0d42fda8b8329e1156c7 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6313 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-22 18:00:56 +02:00
Always load option ROMs if any are found. The decision to run
the ROM is still determined at runtime, but the distinction
device: provide option to always load PCI option roms Certain kernel drivers require the presence of option rom contents because the board's static configuration information is located within the blob. Therefore, allow a chipset/board to instruct the pci device handling code to always load but not necessarily run the option rom. BUG=chrome-os-partner:25885 BRANCH=baytrail TEST=Both enabling and not enabling this option shows expected behavior. Change-Id: Ib0f65ffaf1a861b543573a062c291f4ba491ffe0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188720 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5594 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-05-01 15:31:34 +02:00
between loading and not running comes into play for CHROMEOS.
src/.../Kconfig: various small fixes to texts Fixed spelling and added empty lines to separate the help from the text automatically added during make menuconfig. Change-Id: I6eee2c86e30573deb8cf0d42fda8b8329e1156c7 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6313 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-22 18:00:56 +02:00
An example where this is required is that VBT (Video BIOS Tables)
device: provide option to always load PCI option roms Certain kernel drivers require the presence of option rom contents because the board's static configuration information is located within the blob. Therefore, allow a chipset/board to instruct the pci device handling code to always load but not necessarily run the option rom. BUG=chrome-os-partner:25885 BRANCH=baytrail TEST=Both enabling and not enabling this option shows expected behavior. Change-Id: Ib0f65ffaf1a861b543573a062c291f4ba491ffe0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188720 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5594 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
2014-05-01 15:31:34 +02:00
are needed for the kernel's display driver to know how a piece of
hardware is configured to be used.
Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-10-07 01:47:51 +02:00
config ON_DEVICE_ROM_RUN
bool "Run Option ROMs on PCI devices"
Run option ROMs in coreboot by default only if the payload is not SeaBIOS Change-Id: I29fb86ff3a3187b720ce5ef246c4eeee696ab5cd Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/1637 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-10-27 14:17:04 +02:00
default n if PAYLOAD_SEABIOS
default y if !PAYLOAD_SEABIOS
Allow PCI option rom execution only on systems with PCI support ... on all other systems it will fail terribly ;-) Change-Id: I7f8d10b71b2dbc798b28aee7c36872685c793fd8 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2001 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2012-12-08 00:50:44 +01:00
depends on PCI && !PAYLOAD_SEABIOS || EXPERT
Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-10-07 01:47:51 +02:00
help
Clarify that _ROM_RUN Kconfig options control if ROMs are run by coreboot Also clarify that enabling these options is generally not desirable if using SeaBIOS as payload since the option ROMs are run by SeaBIOS with more complete BIOS interrupt services available than coreboot. Change-Id: Ic4a45c351a4933aedad08d70a088eab04ca35b05 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/1636 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-27 13:45:51 +02:00
Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot.
If disabled, only Option ROMs stored in CBFS will be executed by
coreboot. If you are concerned about security, you might want to
disable this option, but it might leave your system in a state of
degraded functionality.
Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-10-07 01:47:51 +02:00
Clarify that _ROM_RUN Kconfig options control if ROMs are run by coreboot Also clarify that enabling these options is generally not desirable if using SeaBIOS as payload since the option ROMs are run by SeaBIOS with more complete BIOS interrupt services available than coreboot. Change-Id: Ic4a45c351a4933aedad08d70a088eab04ca35b05 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/1636 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-27 13:45:51 +02:00
When using a SeaBIOS payload it runs all option ROMs with much
more complete BIOS interrupt services available than coreboot,
which some option ROMs require in order to function correctly.
Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-10-07 01:47:51 +02:00
Clarify that _ROM_RUN Kconfig options control if ROMs are run by coreboot Also clarify that enabling these options is generally not desirable if using SeaBIOS as payload since the option ROMs are run by SeaBIOS with more complete BIOS interrupt services available than coreboot. Change-Id: Ic4a45c351a4933aedad08d70a088eab04ca35b05 Signed-off-by: Peter Stuge <peter@stuge.se> Reviewed-on: http://review.coreboot.org/1636 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-10-27 13:45:51 +02:00
If unsure, say N when using SeaBIOS as payload, Y otherwise.
Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-10-07 01:47:51 +02:00
Add Kconfig support for PCI option ROMS. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 16:36:12 +02:00
choice
Various Kconfig fixes and improvements: - Add helps texts to multiple user-visible Kconfig options. - Improve some menu and option names. - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down (instead of up) when changing "no payload" to "ELF payload" (more intuitive, IMHO). - s/cbfs/cbfstool/. - Add some TODO items where needed. - Put GDB_STUB in a "Debugging" menu, no options should be top-level. There'll be more debug options later, I'm pretty sure. - Start converting help texts which are not user-visible to #-comments. - Re-order some options for more intuitive menus. - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them. - "Maximum reboot count" should proabably not be user-selectable, or at most if CONFIG_EXPERT (yet to be added) is enabled. It does definately not need its own "Misc options" menu. - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to run option ROMs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:15:40 +02:00
prompt "Option ROM execution type"
- Improve help texts for option ROM initialization methods - disallow REAL_MODE method if ARCH_X86 is not set. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-31 22:46:12 +01:00
default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86
default PCI_OPTION_ROM_RUN_REALMODE if ARCH_X86
Remove PCI_ROM_RUN option The main purpose of option rom is to supply int* handlers. But supplying those is outside of coreboot scope and if someone needs those they should run SeaBIOS anyway which runs the option roms wonderfully. Running VGA oprom is kept because they're needed to init graphics. This patch still keeps the options to include the option roms to make them available to SeaBIOS. Change-Id: I646334cf88094d3bf8f527779a68a07e0b4b93ec Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4545 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2013-12-20 17:47:19 +01:00
depends on VGA_ROM_RUN || GEODE_VSA
Various Kconfig fixes and improvements: - Add helps texts to multiple user-visible Kconfig options. - Improve some menu and option names. - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down (instead of up) when changing "no payload" to "ELF payload" (more intuitive, IMHO). - s/cbfs/cbfstool/. - Add some TODO items where needed. - Put GDB_STUB in a "Debugging" menu, no options should be top-level. There'll be more debug options later, I'm pretty sure. - Start converting help texts which are not user-visible to #-comments. - Re-order some options for more intuitive menus. - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them. - "Maximum reboot count" should proabably not be user-selectable, or at most if CONFIG_EXPERT (yet to be added) is enabled. It does definately not need its own "Misc options" menu. - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to run option ROMs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:15:40 +02:00
config PCI_OPTION_ROM_RUN_REALMODE
YABEL update - drop x86emu + old biosemu in favor of YABEL - Add YABEL_DIRECTHW to get the old biosemu behavior - add support for vesa console using YABEL - add coreboot table entry with console information - add bootsplash support (reads /bootsplash.jpg from CBFS) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Pattrick Hueper <phueper@hueper.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 05:33:13 +01:00
prompt "Native mode"
Various Kconfig fixes and improvements: - Add helps texts to multiple user-visible Kconfig options. - Improve some menu and option names. - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down (instead of up) when changing "no payload" to "ELF payload" (more intuitive, IMHO). - s/cbfs/cbfstool/. - Add some TODO items where needed. - Put GDB_STUB in a "Debugging" menu, no options should be top-level. There'll be more debug options later, I'm pretty sure. - Start converting help texts which are not user-visible to #-comments. - Re-order some options for more intuitive menus. - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them. - "Maximum reboot count" should proabably not be user-selectable, or at most if CONFIG_EXPERT (yet to be added) is enabled. It does definately not need its own "Misc options" menu. - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to run option ROMs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:15:40 +02:00
bool
- Improve help texts for option ROM initialization methods - disallow REAL_MODE method if ARCH_X86 is not set. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-31 22:46:12 +01:00
depends on ARCH_X86
Separate CONFIG_VGA_CONSOLE from CONFIG_VGA_BRIDGE_SETUP. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-17 18:54:46 +02:00
help
Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-10-07 01:47:51 +02:00
If you select this option, PCI Option ROMs will be executed
- Improve help texts for option ROM initialization methods - disallow REAL_MODE method if ARCH_X86 is not set. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-31 22:46:12 +01:00
natively on the CPU in real mode. No CPU emulation is involved,
so this is the fastest, but also the least secure option.
(only works on x86/x64 systems)
Add Kconfig support for PCI option ROMS. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 16:36:12 +02:00
YABEL update - drop x86emu + old biosemu in favor of YABEL - Add YABEL_DIRECTHW to get the old biosemu behavior - add support for vesa console using YABEL - add coreboot table entry with console information - add bootsplash support (reads /bootsplash.jpg from CBFS) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Pattrick Hueper <phueper@hueper.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 05:33:13 +01:00
config PCI_OPTION_ROM_RUN_YABEL
Random cosmetic fixes (trivial). - Fix typos. - Whitespace and consistency fixes. - Make "menuconfig" help easily readable in 80x25 terminals / xterms. - Use full/correct prototype for cbfs_and_run_core() everywhere. - More cosmetic fixes in license headers. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 17:41:49 +01:00
prompt "Secure mode"
Various Kconfig fixes and improvements: - Add helps texts to multiple user-visible Kconfig options. - Improve some menu and option names. - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down (instead of up) when changing "no payload" to "ELF payload" (more intuitive, IMHO). - s/cbfs/cbfstool/. - Add some TODO items where needed. - Put GDB_STUB in a "Debugging" menu, no options should be top-level. There'll be more debug options later, I'm pretty sure. - Start converting help texts which are not user-visible to #-comments. - Re-order some options for more intuitive menus. - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them. - "Maximum reboot count" should proabably not be user-selectable, or at most if CONFIG_EXPERT (yet to be added) is enabled. It does definately not need its own "Misc options" menu. - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to run option ROMs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:15:40 +02:00
bool
Enable PCI_OPTION_ROM_REALMODE when GEODE_VSA is selected. Using YABEL isn't supported for the VSA, so don't allow a choice. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-06-04 17:55:12 +02:00
depends on !GEODE_VSA
Various Kconfig fixes and improvements: - Add helps texts to multiple user-visible Kconfig options. - Improve some menu and option names. - PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down (instead of up) when changing "no payload" to "ELF payload" (more intuitive, IMHO). - s/cbfs/cbfstool/. - Add some TODO items where needed. - Put GDB_STUB in a "Debugging" menu, no options should be top-level. There'll be more debug options later, I'm pretty sure. - Start converting help texts which are not user-visible to #-comments. - Re-order some options for more intuitive menus. - Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them. - "Maximum reboot count" should proabably not be user-selectable, or at most if CONFIG_EXPERT (yet to be added) is enabled. It does definately not need its own "Misc options" menu. - Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to run option ROMs. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-10-07 18:15:40 +02:00
help
- Improve help texts for option ROM initialization methods - disallow REAL_MODE method if ARCH_X86 is not set. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-31 22:46:12 +01:00
If you select this option, the x86emu CPU emulator will be used to
Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-10-07 01:47:51 +02:00
execute PCI Option ROMs.
Random cosmetic fixes (trivial). - Fix typos. - Whitespace and consistency fixes. - Make "menuconfig" help easily readable in 80x25 terminals / xterms. - Use full/correct prototype for cbfs_and_run_core() everywhere. - More cosmetic fixes in license headers. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 17:41:49 +01:00
Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-10-07 01:47:51 +02:00
This option prevents Option ROMs from doing dirty tricks with the
Random cosmetic fixes (trivial). - Fix typos. - Whitespace and consistency fixes. - Make "menuconfig" help easily readable in 80x25 terminals / xterms. - Use full/correct prototype for cbfs_and_run_core() everywhere. - More cosmetic fixes in license headers. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 17:41:49 +01:00
system (such as installing SMM modules or hypervisors), but it is
Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-10-07 01:47:51 +02:00
also significantly slower than the native Option ROM initialization
Random cosmetic fixes (trivial). - Fix typos. - Whitespace and consistency fixes. - Make "menuconfig" help easily readable in 80x25 terminals / xterms. - Use full/correct prototype for cbfs_and_run_core() everywhere. - More cosmetic fixes in license headers. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 17:41:49 +01:00
method.
- Improve help texts for option ROM initialization methods - disallow REAL_MODE method if ARCH_X86 is not set. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5072 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-01-31 22:46:12 +01:00
This is the default choice for non-x86 systems.
Random cosmetic fixes (trivial). - Fix typos. - Whitespace and consistency fixes. - Make "menuconfig" help easily readable in 80x25 terminals / xterms. - Use full/correct prototype for cbfs_and_run_core() everywhere. - More cosmetic fixes in license headers. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 17:41:49 +01:00
YABEL update - drop x86emu + old biosemu in favor of YABEL - Add YABEL_DIRECTHW to get the old biosemu behavior - add support for vesa console using YABEL - add coreboot table entry with console information - add bootsplash support (reads /bootsplash.jpg from CBFS) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Pattrick Hueper <phueper@hueper.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 05:33:13 +01:00
endchoice
Add Kconfig support for PCI option ROMS. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 16:36:12 +02:00
Add two YABEL options to Kconfig Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-12 10:32:17 +01:00
config YABEL_PCI_ACCESS_OTHER_DEVICES
Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-10-07 01:47:51 +02:00
prompt "Allow Option ROMs to access other devices"
Add two YABEL options to Kconfig Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-12 10:32:17 +01:00
bool
depends on PCI_OPTION_ROM_RUN_YABEL
help
Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-10-07 01:47:51 +02:00
Per default, YABEL only allows Option ROMs to access the PCI device
Add two YABEL options to Kconfig Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-12 10:32:17 +01:00
that they are associated with. However, this causes trouble for some
Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-10-07 01:47:51 +02:00
onboard graphics chips whose Option ROM needs to reconfigure the
Random cosmetic fixes (trivial). - Fix typos. - Whitespace and consistency fixes. - Make "menuconfig" help easily readable in 80x25 terminals / xterms. - Use full/correct prototype for cbfs_and_run_core() everywhere. - More cosmetic fixes in license headers. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 17:41:49 +01:00
north bridge.
Add two YABEL options to Kconfig Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-12 10:32:17 +01:00
Allow YABEL to fake write accesses to config space A new Kconfig option tells YABEL to succeed on write accesses on other devices' config space without performing the actual write. This is enough for some basic bus modification done by some Option ROMs. Change-Id: Iab04f3a5c350b96654da4ba26858037f4c4b5c0a Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1249 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-20 13:44:50 +02:00
config YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG
prompt "Fake success on writing other device's config space"
bool
depends on YABEL_PCI_ACCESS_OTHER_DEVICES
help
By default, YABEL aborts when the Option ROM tries to write to other
devices' config spaces. With this option enabled, the write doesn't
follow through, but the Option ROM is allowed to go on.
This can create issues such as hanging Option ROMs (if it depends on
that other register changing to the written value), so test for
impact before using this option.
Add two YABEL options to Kconfig Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-12 10:32:17 +01:00
config YABEL_VIRTMEM_LOCATION
prompt "Location of YABEL's virtual memory"
hex
YABEL update - drop x86emu + old biosemu in favor of YABEL - Add YABEL_DIRECTHW to get the old biosemu behavior - add support for vesa console using YABEL - add coreboot table entry with console information - add bootsplash support (reads /bootsplash.jpg from CBFS) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Pattrick Hueper <phueper@hueper.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 05:33:13 +01:00
depends on PCI_OPTION_ROM_RUN_YABEL && EXPERT
Add two YABEL options to Kconfig Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-12 10:32:17 +01:00
default 0x1000000
help
YABEL requires 1MB memory for its CPU emulation. This memory is
normally located at 16MB.
This patch is from 2009-10-20 Convert all DEBUG_SMBUS, DEBUG_SMI, and DEBUG_RAM_SETUP custom and local #defines into globally configurable kconfig options (and Options.lb options for as long as newconfig still exists) which can be enabled by the user in the "Debugging" menu. The respective menu items only appear if a board is selected where the chipset code actually provides such additional DEBUG output. All three variables default to 0 / off for now. Also, drop a small chunk of dead/useless code in the src/northbridge/via/cn700/raminit.c file, which would otherwise break compilation. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Reworked to still apply to trunk, added X86EMU_DEBUG (and make the x86emu/yabel code only work printf instead of a redefined version of printk and Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5185 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-03-05 11:03:50 +01:00
config YABEL_VIRTMEM_LOCATION
hex
depends on PCI_OPTION_ROM_RUN_YABEL && !EXPERT
default 0x1000000
YABEL update - drop x86emu + old biosemu in favor of YABEL - Add YABEL_DIRECTHW to get the old biosemu behavior - add support for vesa console using YABEL - add coreboot table entry with console information - add bootsplash support (reads /bootsplash.jpg from CBFS) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Pattrick Hueper <phueper@hueper.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 05:33:13 +01:00
config YABEL_DIRECTHW
Random cosmetic fixes (trivial). - Fix typos. - Whitespace and consistency fixes. - Make "menuconfig" help easily readable in 80x25 terminals / xterms. - Use full/correct prototype for cbfs_and_run_core() everywhere. - More cosmetic fixes in license headers. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 17:41:49 +01:00
prompt "Direct hardware access"
YABEL update - drop x86emu + old biosemu in favor of YABEL - Add YABEL_DIRECTHW to get the old biosemu behavior - add support for vesa console using YABEL - add coreboot table entry with console information - add bootsplash support (reads /bootsplash.jpg from CBFS) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Pattrick Hueper <phueper@hueper.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 05:33:13 +01:00
bool
Fix Yabel compilation on non-x86 platforms Mostly preventing inb/outb being used on non-x86 Change-Id: I0434df4ce477c262337672867dc6ce398ff95279 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2002 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-12-08 01:55:12 +01:00
depends on PCI_OPTION_ROM_RUN_YABEL && ARCH_X86
Various Kconfig and Makefile.inc fixes and cosmetics. - Whitespace fixes, remove trailing whitespace, use TABs for identation (except in Kconfig "help" lines, which start with one TAB and two spaces as per Linux kernel style) - Kconfig: Standardize on 'bool' (not 'boolean'). - s/lar/cbfs/ in one Kconfig help string. - Reword various Kconfig menu entries for a more usable and consistent menu. - Fix incorrect comment of NO_RUN in devices/Kconfig. - superio/serverengines/Kconfig: Incorrect config name. - superio/Makefile.inc: s/serverengine/serverengines/. - superio/intel/Kconfig: s/SUPERIO_FINTEK_I3100/SUPERIO_INTEL_I3100/. - mainboard/via/vt8454c/Kconfig: Fix copy-paste error in help string. - mainboard/via/epia-n/Kconfig: Fix "bool" menu text. - console/Kconfig: Don't mention defaults in the menu string, kconfig already displays them anyway. - Kill "Drivers" menu for now, it only confuses users as long as it's emtpy. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-25 02:53:22 +02:00
help
YABEL update - drop x86emu + old biosemu in favor of YABEL - Add YABEL_DIRECTHW to get the old biosemu behavior - add support for vesa console using YABEL - add coreboot table entry with console information - add bootsplash support (reads /bootsplash.jpg from CBFS) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Pattrick Hueper <phueper@hueper.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 05:33:13 +01:00
YABEL consists of two parts: It uses x86emu for the CPU emulation and
Random cosmetic fixes (trivial). - Fix typos. - Whitespace and consistency fixes. - Make "menuconfig" help easily readable in 80x25 terminals / xterms. - Use full/correct prototype for cbfs_and_run_core() everywhere. - More cosmetic fixes in license headers. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 17:41:49 +01:00
additionally provides a PC system emulation that filters bad device
and memory access (such as PCI config space access to other devices
than the initialized one).
YABEL update - drop x86emu + old biosemu in favor of YABEL - Add YABEL_DIRECTHW to get the old biosemu behavior - add support for vesa console using YABEL - add coreboot table entry with console information - add bootsplash support (reads /bootsplash.jpg from CBFS) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Pattrick Hueper <phueper@hueper.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 05:33:13 +01:00
When choosing this option, x86emu will pass through all hardware
Random cosmetic fixes (trivial). - Fix typos. - Whitespace and consistency fixes. - Make "menuconfig" help easily readable in 80x25 terminals / xterms. - Use full/correct prototype for cbfs_and_run_core() everywhere. - More cosmetic fixes in license headers. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5146 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 17:41:49 +01:00
accesses to memory and I/O devices to the underlying memory and I/O
Don't run any Option ROMs stored outside of the system flash Right now coreboot only executes VGA Option ROMs. However, this is not good enough. For security reasons we want to execute only Option ROMs stored in our r/o CBFS. This patch adds a new option to disable execution of arbitrary Option ROMs. Also fix the capitalization of Option ROM in src/devices/Kconfig Change-Id: I485291c06ec5cd1f875357401831fe32ccfc5f2f Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/730 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Mathias Krause <minipli@googlemail.com>
2011-10-07 01:47:51 +02:00
addresses. While this option prevents Option ROMs from doing dirty
YABEL update - drop x86emu + old biosemu in favor of YABEL - Add YABEL_DIRECTHW to get the old biosemu behavior - add support for vesa console using YABEL - add coreboot table entry with console information - add bootsplash support (reads /bootsplash.jpg from CBFS) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Pattrick Hueper <phueper@hueper.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5135 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-02-22 05:33:13 +01:00
tricks with the CPU (such as installing SMM modules or hypervisors),
they can still access all devices in the system.
Enable this option for a good compromise between security and speed.
Printing coreboot debug messages on VGA console is pretty much useless, since initializing VGA happens pretty much as the last thing before starting the payload. Hence, drop VGA console support, as we did in coreboot v3. - Drop VGA and BTEXT console support. Console is meant to be debugging only, and by the time graphics comes up 99% of the risky stuff has already happened. Note: This patch does not remove hardware init but only the actual output functionality. The ragexl driver needs some extra love, but that's for another day - factor out die() and post() - drop some leftover RAMBASE < 0x100000 checks. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: QingPei Wang<wangqingpei@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22 09:09:50 +01:00
config MULTIPLE_VGA_ADAPTERS
Separate CONFIG_VGA_CONSOLE from CONFIG_VGA_BRIDGE_SETUP. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-17 18:54:46 +02:00
bool
default n
gizmosphere/gizmo: Move support of SPD data in CBFS This code is not specific to any board or AGESA family. Change-Id: I26c32fbe8e45018e239762b072dfe3da05271697 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5690 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-05 15:40:15 +02:00
config SPD_CACHE
bool
default n
Create a a new configuration variable for PCI Not all architectures have PCI. This new config variable allows control of whether PCI support is configued in. It is selected for ARCH_X86. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1947 Tested-by: build bot (Jenkins)
2012-11-30 01:28:21 +01:00
config PCI
bool
default n
Move some config variables that are in one or two mainboards to more rational places. The goal is to reduce the number of Config variables defined in mainboard Kconfig files to the absolute minimum. This has the side effect of making SERIAL_POST a menu item, which is nice. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 16:23:38 +02:00
config PCI_64BIT_PREF_MEM
bool
Create a a new configuration variable for PCI Not all architectures have PCI. This new config variable allows control of whether PCI support is configued in. It is selected for ARCH_X86. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1947 Tested-by: build bot (Jenkins)
2012-11-30 01:28:21 +01:00
depends on PCI
Move some config variables that are in one or two mainboards to more rational places. The goal is to reduce the number of Config variables defined in mainboard Kconfig files to the absolute minimum. This has the side effect of making SERIAL_POST a menu item, which is nice. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 16:23:38 +02:00
default n
config HYPERTRANSPORT_PLUGIN_SUPPORT
bool
Create a a new configuration variable for PCI Not all architectures have PCI. This new config variable allows control of whether PCI support is configued in. It is selected for ARCH_X86. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1947 Tested-by: build bot (Jenkins)
2012-11-30 01:28:21 +01:00
depends on PCI
Remove HyperTransport support from boards that don't need it. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-24 17:09:11 +02:00
default n
Move some config variables that are in one or two mainboards to more rational places. The goal is to reduce the number of Config variables defined in mainboard Kconfig files to the absolute minimum. This has the side effect of making SERIAL_POST a menu item, which is nice. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 16:23:38 +02:00
config PCIX_PLUGIN_SUPPORT
bool
Create a a new configuration variable for PCI Not all architectures have PCI. This new config variable allows control of whether PCI support is configued in. It is selected for ARCH_X86. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1947 Tested-by: build bot (Jenkins)
2012-11-30 01:28:21 +01:00
depends on PCI
src/Kconfig: Remove HT-specific options. src/cpu/amd/socket_F/Kconfig: Remove second occurrence of CPU_SOCKET_TYPE. src/mainboard/amd/serengeti_cheetah/Kconfig: Add HT_CHAIN_UNITID_BASE here, since it is board specific. src/mainboard/tyan/s289X/Kconfig: Fix typo and change APIC_ID_OFFSET to match old config. src/devices/Kconfig: Change default value of *_PLUGIN_SUPPORT to match old config. src/southbridge/amd/amd8131/Makefile.inc: Remove check since it was a typo, and the correct variable is checked in the parent directory. src/Makefile:Use devicetree.cb instead of Config.lb to generate static.c. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 23:29:32 +02:00
default y
Move some config variables that are in one or two mainboards to more rational places. The goal is to reduce the number of Config variables defined in mainboard Kconfig files to the absolute minimum. This has the side effect of making SERIAL_POST a menu item, which is nice. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 16:23:38 +02:00
config PCIEXP_PLUGIN_SUPPORT
bool
Create a a new configuration variable for PCI Not all architectures have PCI. This new config variable allows control of whether PCI support is configued in. It is selected for ARCH_X86. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1947 Tested-by: build bot (Jenkins)
2012-11-30 01:28:21 +01:00
depends on PCI
src/Kconfig: Remove HT-specific options. src/cpu/amd/socket_F/Kconfig: Remove second occurrence of CPU_SOCKET_TYPE. src/mainboard/amd/serengeti_cheetah/Kconfig: Add HT_CHAIN_UNITID_BASE here, since it is board specific. src/mainboard/tyan/s289X/Kconfig: Fix typo and change APIC_ID_OFFSET to match old config. src/devices/Kconfig: Change default value of *_PLUGIN_SUPPORT to match old config. src/southbridge/amd/amd8131/Makefile.inc: Remove check since it was a typo, and the correct variable is checked in the parent directory. src/Makefile:Use devicetree.cb instead of Config.lb to generate static.c. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 23:29:32 +02:00
default y
Move some config variables that are in one or two mainboards to more rational places. The goal is to reduce the number of Config variables defined in mainboard Kconfig files to the absolute minimum. This has the side effect of making SERIAL_POST a menu item, which is nice. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-08-28 16:23:38 +02:00
config CARDBUS_PLUGIN_SUPPORT
bool
Create a a new configuration variable for PCI Not all architectures have PCI. This new config variable allows control of whether PCI support is configued in. It is selected for ARCH_X86. Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: Ic5fe777b14fd6a16ba605ada1e22acf3e8a2c783 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/1947 Tested-by: build bot (Jenkins)
2012-11-30 01:28:21 +01:00
depends on PCI
src/Kconfig: Remove HT-specific options. src/cpu/amd/socket_F/Kconfig: Remove second occurrence of CPU_SOCKET_TYPE. src/mainboard/amd/serengeti_cheetah/Kconfig: Add HT_CHAIN_UNITID_BASE here, since it is board specific. src/mainboard/tyan/s289X/Kconfig: Fix typo and change APIC_ID_OFFSET to match old config. src/devices/Kconfig: Change default value of *_PLUGIN_SUPPORT to match old config. src/southbridge/amd/amd8131/Makefile.inc: Remove check since it was a typo, and the correct variable is checked in the parent directory. src/Makefile:Use devicetree.cb instead of Config.lb to generate static.c. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2009-09-22 23:29:32 +02:00
default y
Add support for enabling PCIe Common Clock and ASPM These are guarded by individual Kconfig entries. The deprecated CONFIG_PCIE_TUNING defines have been removed in favor of using specific config options. This is the generic half, there is board-specific pieces still to come that tune before and after ASPM is enabled. Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/735 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2011-10-25 23:15:11 +02:00
Add a generic Intel HD audio (Azalia) module azalia_device.c This module uses cim_verb_data to detect and initialize HD audio codecs. The module source code is based on southbridge/intel/sch/audio.c and southbridge/nvidia/mcp55/azalia.c. Change-Id: I810fef6fdcf55d66f62da58c3d7d99f006559d6e Signed-off-by: Andrew Wu <arw@dmp.com.tw> Reviewed-on: http://review.coreboot.org/3844 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-08-12 14:07:47 +02:00
config AZALIA_PLUGIN_SUPPORT
bool
depends on PCI
default n
Add support for enabling PCIe Common Clock and ASPM These are guarded by individual Kconfig entries. The deprecated CONFIG_PCIE_TUNING defines have been removed in favor of using specific config options. This is the generic half, there is board-specific pieces still to come that tune before and after ASPM is enabled. Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/735 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2011-10-25 23:15:11 +02:00
config PCIEXP_COMMON_CLOCK
prompt "Enable PCIe Common Clock"
bool
Make PCIe config options depend on PCIe support Change-Id: I42452a044dc75e35876fcea1736481e538eed663 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2100 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04 19:07:28 +01:00
depends on PCIEXP_PLUGIN_SUPPORT
Add support for enabling PCIe Common Clock and ASPM These are guarded by individual Kconfig entries. The deprecated CONFIG_PCIE_TUNING defines have been removed in favor of using specific config options. This is the generic half, there is board-specific pieces still to come that tune before and after ASPM is enabled. Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/735 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2011-10-25 23:15:11 +02:00
default n
help
Detect and enable Common Clock on PCIe links.
config PCIEXP_ASPM
prompt "Enable PCIe ASPM"
bool
Make PCIe config options depend on PCIe support Change-Id: I42452a044dc75e35876fcea1736481e538eed663 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/2100 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-04 19:07:28 +01:00
depends on PCIEXP_PLUGIN_SUPPORT
Add support for enabling PCIe Common Clock and ASPM These are guarded by individual Kconfig entries. The deprecated CONFIG_PCIE_TUNING defines have been removed in favor of using specific config options. This is the generic half, there is board-specific pieces still to come that tune before and after ASPM is enabled. Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: http://review.coreboot.org/735 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2011-10-25 23:15:11 +02:00
default n
help
Detect and enable ASPM on PCIe links.
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
device/pciexp: Add support for PCIe CLK power management Set PCIe "Enable Clock Power Management", if endpoint supports it. BUG=chrome-os-partner:31424 BRANCH=none TEST=build and boot on rambi, check Enable Clock Power Management in link control register is set properly Change-Id: Ie54110d1ef42184cfcf47c9fe4d735960aebe47f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://chromium-review.googlesource.com/220742 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> [Edit commit message.] Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/8447 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-01 05:13:54 +02:00
config PCIEXP_CLK_PM
prompt "Enable PCIe Clock Power Management"
bool
depends on PCIEXP_PLUGIN_SUPPORT
default n
help
Detect and enable Clock Power Management on PCIe.
OxPCIe uart: Split PCI bridge control None of the PCI bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid, fill samsung/lumpy with working values. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5237 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-14 11:45:09 +01:00
config EARLY_PCI_BRIDGE
bool "Early PCI bridge"
depends on PCI
default n
help
While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system.
This option enables static configuration for a single pre-defined
PCI bridge function on bus 0.
PCIe: Add L1 Sub-State support. Enable L1 Sub-State when both root port and endpoint support it. [pg: keyed the feature to MMCONF_SUPPORT, otherwise boards without that capability fail to build.] Change-Id: Id11fc7c73eb865411747eef63f5f901e00a17f84 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6ac04ad7e2261846e40da297f7fa317ccebda092 Original-BUG=chrome-os-partner:31424 Original-TEST=Build a image and run on Samus proto boards to check if the settings are applied correctly. I just only have proto boards and need someone having EVT boards to confirm the settings. Original-Signed-off-by: Kenji Chen <kenji.chen@intel.com> Original-Change-Id: Id1b5a52ff0b896f4531c4a6e68e70a2cea8c736a Original-Reviewed-on: https://chromium-review.googlesource.com/221436 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/8832 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-10-03 19:14:44 +02:00
config PCIEXP_L1_SUB_STATE
prompt "Enable PCIe ASPM L1 SubState"
bool
depends on PCIEXP_PLUGIN_SUPPORT && MMCONF_SUPPORT
default n
help
Detect and enable ASPM on PCIe links.
OxPCIe uart: Split PCI bridge control None of the PCI bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid, fill samsung/lumpy with working values. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5237 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-14 11:45:09 +01:00
if EARLY_PCI_BRIDGE
config EARLY_PCI_BRIDGE_DEVICE
hex "bridge device"
default 0x0
config EARLY_PCI_BRIDGE_FUNCTION
hex "bridge function"
default 0x0
config EARLY_PCI_MMIO_BASE
hex "MMIO window base"
default 0x0
endif # EARLY_PCI_BRIDGE
Kconfig: clean up options in top level and device menu Move generic options to the "General Setup" menu. Move device specific options to the "Devices" menu. Change-Id: I514a021305d43f026b24fd3016477300700ed401 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7089 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-17 13:08:36 +02:00
config SUBSYSTEM_VENDOR_ID
hex "Override PCI Subsystem Vendor ID"
depends on PCI
default "0x0000"
help
This config option will override the devicetree settings for
PCI Subsystem Vendor ID.
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
Kconfig: clean up options in top level and device menu Move generic options to the "General Setup" menu. Move device specific options to the "Devices" menu. Change-Id: I514a021305d43f026b24fd3016477300700ed401 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7089 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-17 13:08:36 +02:00
config SUBSYSTEM_DEVICE_ID
hex "Override PCI Subsystem Device ID"
depends on PCI
default "0x0000"
help
This config option will override the devicetree settings for
PCI Subsystem Device ID.
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
config VGA_BIOS
bool "Add a VGA BIOS image"
help
Select this option if you have a VGA BIOS image that you would
like to add to your ROM.
You will be able to specify the location and file name of the
image later.
config VGA_BIOS_FILE
string "VGA BIOS path and filename"
depends on VGA_BIOS
default "vgabios.bin"
help
The path and filename of the file to use as VGA BIOS.
config VGA_BIOS_ID
string "VGA device PCI IDs"
depends on VGA_BIOS
default "1106,3230"
help
The comma-separated PCI vendor and device ID that would associate
your VGA BIOS to your video card.
Example: 1106,3230
In the above example 1106 is the PCI vendor ID (in hex, but without
the "0x" prefix) and 3230 specifies the PCI device ID of the
video card (also in hex, without "0x" prefix).
src/device/Kconfig: make help for VGA_BIOS_ID and PXE_ROM_ID more similar Add to VGA_BIOS_ID the hint about lspci -nn and add to PXE_ROM_ID an empty line at the end for better readability in menuconfig. Change-Id: I56751c047c1ff08142e2af58ef3ba5fe1169eba5 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6301 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-17 11:59:41 +02:00
Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
config INTEL_MBI
bool "Add an MBI image"
depends on NORTHBRIDGE_INTEL_I82830
help
Select this option if you have an Intel MBI image that you would
like to add to your ROM.
You will be able to specify the location and file name of the
image later.
config MBI_FILE
string "Intel MBI path and filename"
depends on INTEL_MBI
default "mbi.bin"
help
The path and filename of the file to use as VGA BIOS.
Kconfig: clean up options in top level and device menu Move generic options to the "General Setup" menu. Move device specific options to the "Devices" menu. Change-Id: I514a021305d43f026b24fd3016477300700ed401 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7089 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2014-10-17 13:08:36 +02:00
config PXE_ROM
bool "Add a PXE ROM image"
help
Select this option if you have a PXE ROM image that you would
like to add to your ROM.
config PXE_ROM_FILE
string "PXE ROM filename"
depends on PXE_ROM
default "pxe.rom"
help
The path and filename of the file to use as PXE ROM.
config PXE_ROM_ID
string "network card PCI IDs"
depends on PXE_ROM
default "10ec,8168"
help
The comma-separated PCI vendor and device ID that would associate
your PXE ROM to your network card.
Example: 10ec,8168
In the above example 10ec is the PCI vendor ID (in hex, but without
the "0x" prefix) and 8168 specifies the PCI device ID of the
network card (also in hex, without "0x" prefix).
Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.
i2c: Add software_i2c driver for I2C debugging and emulation This patch adds I2C emulation in software through raw toggling of the SDA/SCL lines. Platforms need to provide bindings to toggle their respective I2C busses for this to work (e.g. by pinmuxing them as GPIOs, currently only enabled for Tegra). This is mostly useful as a debugging feature, to drive unusual states on a bus and closely monitor the device output without the need of a bus analyzer. It provides a few functions to "wedge" an I2C bus by aborting a transaction at certain points, which can be used to test if a system can correctly recover from an ill-timed reboot. However, it can also dynamically replace the existing I2C transfer functions and drive some/all I2C transfers on the system, which might be useful if a driver for the actual I2C controller hardware is not (yet) available. Based on original code by Doug Anderson <dianders@chromium.org> and Hung-ying Tyan <tyanh@chromium.org> for the ChromeOS embedded controller project. BRANCH=None BUG=chrome-os-partner:28323 TEST=Spread tegra_software_i2c_init()/tegra_software_i2c_disable() through the code and see that everything still works. Original-Change-Id: I9ee7ccbd1efb38206669a35d0c3318af16f8be63 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/198791 Original-Reviewed-by: Doug Anderson <dianders@chromium.org> Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org> (cherry picked from commit 8f71503dbbd74c5298e90e2163b67d4efe3e89db) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: Id6c5f75bb5baaabd62b6b1fc26c2c71d9f1ce682 Reviewed-on: http://review.coreboot.org/7947 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-05-06 03:03:46 +02:00
config SOFTWARE_I2C
bool "Enable I2C controller emulation in software"
default n
help
This config option will enable code to override the i2c_transfer
routine with a (simple) software emulation of the protocol. This may
be useful for debugging or on platforms where a driver for the real
I2C controller is not (yet) available. The platform code needs to
provide bindings to manually toggle I2C lines.
Fix Kconfig whitespace Change-Id: Iad64d018edda3064a77bfbcd41cfea5275a2e737 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8013 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-12-31 09:36:08 +01:00
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
endmenu
menu "Display"
Google Link: Add remaining code to support native graphics The Link native graphics commit 49428d84 [1] Add support for Google's Chromebook Pixel was missing some of the higher level bits, and hence could not be used. This is not new code -- it has been working since last August -- so the effort now is to get it into the tree and structure it in a way compatible with upstream coreboot. 1. Add options to src/device/Kconfig to enable native graphics. 2. Export the MTRR function for setting variable MTRRs. 3. Clean up some of the comments and white space. While I realize that the product name is Pixel, the mainboard in the coreboot tree is called Link, and that name is what we will use in our commits. [1] http://review.coreboot.org/2482 Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2531 Tested-by: build bot (Jenkins)
2013-02-26 19:07:40 +01:00
depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || MAINBOARD_DO_NATIVE_VGA_INIT
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
config FRAMEBUFFER_SET_VESA_MODE
Google Link: Add remaining code to support native graphics The Link native graphics commit 49428d84 [1] Add support for Google's Chromebook Pixel was missing some of the higher level bits, and hence could not be used. This is not new code -- it has been working since last August -- so the effort now is to get it into the tree and structure it in a way compatible with upstream coreboot. 1. Add options to src/device/Kconfig to enable native graphics. 2. Export the MTRR function for setting variable MTRRs. 3. Clean up some of the comments and white space. While I realize that the product name is Pixel, the mainboard in the coreboot tree is called Link, and that name is what we will use in our commits. [1] http://review.coreboot.org/2482 Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2531 Tested-by: build bot (Jenkins)
2013-02-26 19:07:40 +01:00
prompt "Set framebuffer graphics resolution"
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
bool
depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
help
Google Link: Add remaining code to support native graphics The Link native graphics commit 49428d84 [1] Add support for Google's Chromebook Pixel was missing some of the higher level bits, and hence could not be used. This is not new code -- it has been working since last August -- so the effort now is to get it into the tree and structure it in a way compatible with upstream coreboot. 1. Add options to src/device/Kconfig to enable native graphics. 2. Export the MTRR function for setting variable MTRRs. 3. Clean up some of the comments and white space. While I realize that the product name is Pixel, the mainboard in the coreboot tree is called Link, and that name is what we will use in our commits. [1] http://review.coreboot.org/2482 Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2531 Tested-by: build bot (Jenkins)
2013-02-26 19:07:40 +01:00
Set VESA/native framebuffer mode (needed for bootsplash and graphical framebuffer console)
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
choice
Google Link: Add remaining code to support native graphics The Link native graphics commit 49428d84 [1] Add support for Google's Chromebook Pixel was missing some of the higher level bits, and hence could not be used. This is not new code -- it has been working since last August -- so the effort now is to get it into the tree and structure it in a way compatible with upstream coreboot. 1. Add options to src/device/Kconfig to enable native graphics. 2. Export the MTRR function for setting variable MTRRs. 3. Clean up some of the comments and white space. While I realize that the product name is Pixel, the mainboard in the coreboot tree is called Link, and that name is what we will use in our commits. [1] http://review.coreboot.org/2482 Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2531 Tested-by: build bot (Jenkins)
2013-02-26 19:07:40 +01:00
prompt "framebuffer graphics resolution"
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
default FRAMEBUFFER_VESA_MODE_117
device: Do not show "framebuffer graphics resolution" with native init. No native init uses this. Real hardware ones use mode specified in EDID. Qemu one uses CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_[XY]RES. Change-Id: I0845fec10b9811e2be44b5be30b9dc4f1c9719a6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5281 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-21 08:38:27 +01:00
depends on FRAMEBUFFER_SET_VESA_MODE
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
help
This option sets the resolution used for the coreboot framebuffer (and
bootsplash screen).
config FRAMEBUFFER_VESA_MODE_100
bool "640x400 256-color"
config FRAMEBUFFER_VESA_MODE_101
bool "640x480 256-color"
config FRAMEBUFFER_VESA_MODE_102
bool "800x600 16-color"
config FRAMEBUFFER_VESA_MODE_103
bool "800x600 256-color"
config FRAMEBUFFER_VESA_MODE_104
bool "1024x768 16-color"
config FRAMEBUFFER_VESA_MODE_105
src/device/Kconfig: fix typo in label "1024x768 256-color" It had an extraneous digit after 768. Change-Id: Ie415e365f3eac0ed326786cea4c4628c002c4762 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6306 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-19 15:40:40 +02:00
bool "1024x768 256-color"
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
config FRAMEBUFFER_VESA_MODE_106
bool "1280x1024 16-color"
config FRAMEBUFFER_VESA_MODE_107
bool "1280x1024 256-color"
config FRAMEBUFFER_VESA_MODE_108
bool "80x60 text"
config FRAMEBUFFER_VESA_MODE_109
bool "132x25 text"
config FRAMEBUFFER_VESA_MODE_10A
bool "132x43 text"
config FRAMEBUFFER_VESA_MODE_10B
bool "132x50 text"
config FRAMEBUFFER_VESA_MODE_10C
bool "132x60 text"
config FRAMEBUFFER_VESA_MODE_10D
bool "320x200 32k-color (1:5:5:5)"
config FRAMEBUFFER_VESA_MODE_10E
bool "320x200 64k-color (5:6:5)"
config FRAMEBUFFER_VESA_MODE_10F
bool "320x200 16.8M-color (8:8:8)"
config FRAMEBUFFER_VESA_MODE_110
bool "640x480 32k-color (1:5:5:5)"
config FRAMEBUFFER_VESA_MODE_111
bool "640x480 64k-color (5:6:5)"
config FRAMEBUFFER_VESA_MODE_112
bool "640x480 16.8M-color (8:8:8)"
config FRAMEBUFFER_VESA_MODE_113
bool "800x600 32k-color (1:5:5:5)"
config FRAMEBUFFER_VESA_MODE_114
bool "800x600 64k-color (5:6:5)"
config FRAMEBUFFER_VESA_MODE_115
bool "800x600 16.8M-color (8:8:8)"
config FRAMEBUFFER_VESA_MODE_116
bool "1024x768 32k-color (1:5:5:5)"
config FRAMEBUFFER_VESA_MODE_117
bool "1024x768 64k-color (5:6:5)"
config FRAMEBUFFER_VESA_MODE_118
bool "1024x768 16.8M-color (8:8:8)"
config FRAMEBUFFER_VESA_MODE_119
bool "1280x1024 32k-color (1:5:5:5)"
config FRAMEBUFFER_VESA_MODE_11A
bool "1280x1024 64k-color (5:6:5)"
config FRAMEBUFFER_VESA_MODE_11B
bool "1280x1024 16.8M-color (8:8:8)"
config FRAMEBUFFER_VESA_MODE_USER
bool "Manually select VESA mode"
Google Link: Add remaining code to support native graphics The Link native graphics commit 49428d84 [1] Add support for Google's Chromebook Pixel was missing some of the higher level bits, and hence could not be used. This is not new code -- it has been working since last August -- so the effort now is to get it into the tree and structure it in a way compatible with upstream coreboot. 1. Add options to src/device/Kconfig to enable native graphics. 2. Export the MTRR function for setting variable MTRRs. 3. Clean up some of the comments and white space. While I realize that the product name is Pixel, the mainboard in the coreboot tree is called Link, and that name is what we will use in our commits. [1] http://review.coreboot.org/2482 Change-Id: Ie4db21f245cf5062fe3a8ee913d05dd79030e3e8 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/2531 Tested-by: build bot (Jenkins)
2013-02-26 19:07:40 +01:00
depends on !MAINBOARD_DO_NATIVE_VGA_INIT
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
endchoice
# Map the config names to an integer (KB).
config FRAMEBUFFER_VESA_MODE
prompt "VESA mode" if FRAMEBUFFER_VESA_MODE_USER
hex
default 0x100 if FRAMEBUFFER_VESA_MODE_100
default 0x101 if FRAMEBUFFER_VESA_MODE_101
default 0x102 if FRAMEBUFFER_VESA_MODE_102
default 0x103 if FRAMEBUFFER_VESA_MODE_103
default 0x104 if FRAMEBUFFER_VESA_MODE_104
default 0x105 if FRAMEBUFFER_VESA_MODE_105
default 0x106 if FRAMEBUFFER_VESA_MODE_106
default 0x107 if FRAMEBUFFER_VESA_MODE_107
default 0x108 if FRAMEBUFFER_VESA_MODE_108
default 0x109 if FRAMEBUFFER_VESA_MODE_109
default 0x10A if FRAMEBUFFER_VESA_MODE_10A
default 0x10B if FRAMEBUFFER_VESA_MODE_10B
default 0x10C if FRAMEBUFFER_VESA_MODE_10C
default 0x10D if FRAMEBUFFER_VESA_MODE_10D
default 0x10E if FRAMEBUFFER_VESA_MODE_10E
default 0x10F if FRAMEBUFFER_VESA_MODE_10F
default 0x110 if FRAMEBUFFER_VESA_MODE_110
default 0x111 if FRAMEBUFFER_VESA_MODE_111
default 0x112 if FRAMEBUFFER_VESA_MODE_112
default 0x113 if FRAMEBUFFER_VESA_MODE_113
default 0x114 if FRAMEBUFFER_VESA_MODE_114
default 0x115 if FRAMEBUFFER_VESA_MODE_115
default 0x116 if FRAMEBUFFER_VESA_MODE_116
default 0x117 if FRAMEBUFFER_VESA_MODE_117
default 0x118 if FRAMEBUFFER_VESA_MODE_118
default 0x119 if FRAMEBUFFER_VESA_MODE_119
default 0x11A if FRAMEBUFFER_VESA_MODE_11A
default 0x11B if FRAMEBUFFER_VESA_MODE_11B
default 0x117 if FRAMEBUFFER_VESA_MODE_USER
config FRAMEBUFFER_KEEP_VESA_MODE
prompt "Keep VESA framebuffer"
bool
devices: Allow to configure textmode in native gfx init. Usefull to select between text mode which offers best compatibility with payloads and gfx mode which makes the best-looking screen. Also right now we have an unfortunate situation when qemu is in gfx mode while most real systems use text mode. Change-Id: Ifad7ba197875edfdd06eb932afeb5800229ef055 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5282 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-02-22 10:34:47 +01:00
depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || (MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG && MAINBOARD_DO_NATIVE_VGA_INIT)
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
help
This option keeps the framebuffer mode set after coreboot finishes
execution. If this option is enabled, coreboot will pass a
framebuffer entry in its coreboot table and the payload will need a
framebuffer driver. If this option is disabled, coreboot will switch
back to text mode before handing control to a payload.
config BOOTSPLASH
prompt "Show graphical bootsplash"
bool
depends on FRAMEBUFFER_SET_VESA_MODE
help
src/.../Kconfig: various small fixes to texts Fixed spelling and added empty lines to separate the help from the text automatically added during make menuconfig. Change-Id: I6eee2c86e30573deb8cf0d42fda8b8329e1156c7 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6313 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-22 18:00:56 +02:00
This option shows a graphical bootsplash screen. The graphics are
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
loaded from the CBFS file bootsplash.jpg.
src/.../Kconfig: various small fixes to texts Fixed spelling and added empty lines to separate the help from the text automatically added during make menuconfig. Change-Id: I6eee2c86e30573deb8cf0d42fda8b8329e1156c7 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6313 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-22 18:00:56 +02:00
You will be able to specify the location and file name of the
image later.
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
config BOOTSPLASH_FILE
string "Bootsplash path and filename"
depends on BOOTSPLASH
default "bootsplash.jpg"
help
The path and filename of the file to use as graphical bootsplash
screen. The file format has to be jpg.
src/.../Kconfig: various small fixes to texts Fixed spelling and added empty lines to separate the help from the text automatically added during make menuconfig. Change-Id: I6eee2c86e30573deb8cf0d42fda8b8329e1156c7 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6313 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-22 18:00:56 +02:00
Clean up Kconfig - move VGA handling options into devices/Kconfig - make Devices a top level menu - move some options "closer" to the code they control Change-Id: Ia79541d18b2b0d9b89a8b154255e312060627c48 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/1840 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-14 02:00:01 +01:00
endmenu