2016-05-15 22:52:36 +02:00
|
|
|
/*
|
|
|
|
* This file is part of the coreboot project.
|
|
|
|
*
|
|
|
|
* Copyright (C) 2016 Intel Corp.
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License as published by
|
|
|
|
* the Free Software Foundation; version 2 of the License.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope that it will be useful,
|
|
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
|
|
* GNU General Public License for more details.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <arch/io.h>
|
|
|
|
#include <console/console.h>
|
2016-07-25 16:41:54 +02:00
|
|
|
#include <soc/car.h>
|
2016-05-15 22:52:36 +02:00
|
|
|
#include <soc/ramstage.h>
|
2016-05-16 00:05:56 +02:00
|
|
|
#include "reg_access.h"
|
2016-05-15 22:52:36 +02:00
|
|
|
#include "gen1.h"
|
|
|
|
#include "gen2.h"
|
|
|
|
|
2016-05-31 00:01:06 +02:00
|
|
|
void car_mainboard_pre_console_init(void)
|
|
|
|
{
|
|
|
|
const struct reg_script *script;
|
|
|
|
|
|
|
|
/* Initialize the GPIO controllers */
|
|
|
|
if (IS_ENABLED(CONFIG_GALILEO_GEN2))
|
|
|
|
script = gen2_gpio_init;
|
|
|
|
else
|
|
|
|
script = gen1_gpio_init;
|
|
|
|
reg_script_run(script);
|
|
|
|
|
|
|
|
/* Initialize the RXD and TXD paths for UART0 */
|
|
|
|
if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0)) {
|
|
|
|
if (IS_ENABLED(CONFIG_GALILEO_GEN2))
|
|
|
|
script = gen2_hsuart0;
|
|
|
|
else
|
2016-07-25 16:41:54 +02:00
|
|
|
script = (reg_legacy_gpio_read(
|
|
|
|
R_QNC_GPIO_RGLVL_RESUME_WELL)
|
2016-05-31 00:01:06 +02:00
|
|
|
& GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)
|
2016-06-18 18:54:43 +02:00
|
|
|
? gen1_hsuart0_0x20 : gen1_hsuart0_0x21;
|
2016-05-31 00:01:06 +02:00
|
|
|
reg_script_run(script);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-05-16 00:05:56 +02:00
|
|
|
void mainboard_gpio_i2c_init(device_t dev)
|
|
|
|
{
|
|
|
|
const struct reg_script *script;
|
|
|
|
|
|
|
|
printk(BIOS_INFO, "Galileo I2C chip initialization\n");
|
|
|
|
|
|
|
|
/* Determine the correct script for the board */
|
|
|
|
if (IS_ENABLED(CONFIG_GALILEO_GEN2))
|
|
|
|
script = gen2_i2c_init;
|
|
|
|
else
|
|
|
|
/* Determine which I2C address is in use */
|
|
|
|
script = (reg_legacy_gpio_read (R_QNC_GPIO_RGLVL_RESUME_WELL)
|
|
|
|
& GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)
|
2016-06-18 18:54:43 +02:00
|
|
|
? gen1_i2c_0x20_init : gen1_i2c_0x21_init;
|
2016-05-16 00:05:56 +02:00
|
|
|
|
|
|
|
/* Initialize the I2C chips */
|
|
|
|
reg_script_run(script);
|
|
|
|
}
|
|
|
|
|
2016-04-30 00:16:54 +02:00
|
|
|
void mainboard_gpio_pcie_reset(uint32_t pin_value)
|
|
|
|
{
|
|
|
|
uint32_t pin_number;
|
|
|
|
uint32_t value;
|
|
|
|
|
|
|
|
/* Determine the correct PCIe reset pin */
|
|
|
|
if (IS_ENABLED(CONFIG_GALILEO_GEN2))
|
|
|
|
pin_number = GEN2_PCI_RESET_RESUMEWELL_GPIO;
|
|
|
|
else
|
|
|
|
pin_number = GEN1_PCI_RESET_RESUMEWELL_GPIO;
|
|
|
|
|
|
|
|
/* Update the PCIe reset value */
|
|
|
|
value = reg_legacy_gpio_read(R_QNC_GPIO_RGLVL_RESUME_WELL);
|
|
|
|
value = (value & ~(1 << pin_number)) | ((pin_value & 1) << pin_number);
|
|
|
|
reg_legacy_gpio_write(R_QNC_GPIO_RGLVL_RESUME_WELL, value);
|
|
|
|
}
|