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coreboot-kgpe-d16/src/mainboard/purism/librem_bdw/devicetree.cb

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purism/librem_bdl: Add support for Librem 15 v2 Adding new librem_bdl variant for the Librem 15 v2, which is very similar to Librem 13 v1, with the following differences: - SATA ports 0 and 1 instead of 0 and 3 - SATA DTLE IOBP value is 7 instead of 9 for port 0 - There is no LAN device - There are two SODIMM slots, and DQs are interleaved - USB ports are different Change-Id: Ifaca382a540d085e6c919daa992a0fbd52643a5b Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/26184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09 01:34:21 +02:00
chip soc/intel/broadwell
# Enable eDP Hotplug with 6ms pulse
register "gpu_dp_d_hotplug" = "0x06"
# Enable DDI1 Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
nb/intel/hsw,soc/intel/{bdw,skl,apl},mb/*: unify dt panel settings There are multiple different devicetree setting formats for graphics panel settings present in coreboot. Replace the ones for the platforms that already have (mostly) unified gma/graphics setup code by a unified struct in the gma driver. Hook it up in HSW, BDW, SKL, and APL and adapt the devicetrees accordingly. Always ensure that values don't overflow by applying appropriate masks. The remaining platforms implementing panel settings (GM45, i945, ILK and SNB) can be migrated later after unifying their gma/graphics setup code. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-28 00:49:33 +01:00
register "panel_cfg" = "{
.up_delay_ms = 200,
.down_delay_ms = 50,
.cycle_delay_ms = 500,
.backlight_on_delay_ms = 200,
.backlight_off_delay_ms = 200,
.backlight_pwm_hz = 200,
}"
purism/librem_bdl: Add support for Librem 15 v2 Adding new librem_bdl variant for the Librem 15 v2, which is very similar to Librem 13 v1, with the following differences: - SATA ports 0 and 1 instead of 0 and 3 - SATA DTLE IOBP value is 7 instead of 9 for port 0 - There is no LAN device - There are two SODIMM slots, and DQs are interleaved - USB ports are different Change-Id: Ifaca382a540d085e6c919daa992a0fbd52643a5b Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/26184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09 01:34:21 +02:00
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio
mb/purism/librem_bdw: Prepare devicetree for PCH split Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I0fe6de35f7471ce173df40db1444153623544f00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46705 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 20:41:09 +02:00
soc/intel/broadwell: Separate PCH in devicetree Flesh out the PCH configuration into a separate chip. Keep it within the Broadwell SoC directory for now, to ease moving files around. The boards were prepared beforehand and the devicetrees require next to no changes. Tested on out-of-tree Acer Aspire E5-573, still boots. Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46700 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 20:38:23 +02:00
chip soc/intel/broadwell/pch
mb/purism/librem_bdw: Prepare devicetree for PCH split Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I0fe6de35f7471ce173df40db1444153623544f00 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46705 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 20:41:09 +02:00
# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
register "gen1_dec" = "0x00000381"
register "gen2_dec" = "0x000c0081"
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
device pci 15.0 off end # Serial I/O DMA
device pci 15.1 off end # I2C0
device pci 15.2 off end # I2C1
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1
device pci 15.5 off end # UART0
device pci 15.6 off end # UART1
device pci 16.0 off end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 17.0 off end # SDIO
device pci 19.0 off end # GbE
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 off end # PCIe Port #3 - LAN
device pci 1c.3 on end # PCIe Port #4 - WiFi
device pci 1c.4 on end # PCIe Port #5
device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe
device pci 1d.0 off end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on end # LPC bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 on end # SMBus
device pci 1f.6 off end # Thermal
soc/intel/broadwell: Separate PCH in devicetree Flesh out the PCH configuration into a separate chip. Keep it within the Broadwell SoC directory for now, to ease moving files around. The boards were prepared beforehand and the devicetrees require next to no changes. Tested on out-of-tree Acer Aspire E5-573, still boots. Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46700 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-10-23 20:38:23 +02:00
end
purism/librem_bdl: Add support for Librem 15 v2 Adding new librem_bdl variant for the Librem 15 v2, which is very similar to Librem 13 v1, with the following differences: - SATA ports 0 and 1 instead of 0 and 3 - SATA DTLE IOBP value is 7 instead of 9 for port 0 - There is no LAN device - There are two SODIMM slots, and DQs are interleaved - USB ports are different Change-Id: Ifaca382a540d085e6c919daa992a0fbd52643a5b Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/26184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-05-09 01:34:21 +02:00
end
end
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