2012-12-08 02:18:43 +01:00
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# Warning: This file is included whether or not the if is here.
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# The if controls how the evaluation occurs.
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# (See also src/Kconfig)
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2015-04-04 01:58:28 +02:00
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source "src/cpu/*/Kconfig"
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2009-08-12 17:00:51 +02:00
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2014-04-23 00:16:54 +02:00
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if ARCH_X86
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2010-08-30 19:53:13 +02:00
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config CACHE_AS_RAM
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2009-08-27 14:10:50 +02:00
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bool
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2018-06-04 00:28:41 +02:00
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default y
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2009-08-27 14:10:50 +02:00
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2017-04-07 22:20:14 +02:00
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config NO_CAR_GLOBAL_MIGRATION
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bool
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default n
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depends on CACHE_AS_RAM
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help
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This option is selected if there is no need to migrate CAR globals.
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All stages which use CAR globals can directly access the variables
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from their linked addresses.
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2009-08-12 17:00:51 +02:00
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config DCACHE_RAM_BASE
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hex
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config DCACHE_RAM_SIZE
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hex
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2015-06-02 20:47:36 +02:00
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config DCACHE_BSP_STACK_SIZE
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hex
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2015-06-03 03:25:03 +02:00
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config DCACHE_BSP_STACK_SLUSH
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hex
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2015-06-02 20:47:36 +02:00
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config DCACHE_AP_STACK_SIZE
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hex
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2009-08-12 17:00:51 +02:00
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config SMP
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bool
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2009-09-22 20:49:08 +02:00
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default y if MAX_CPUS != 1
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2009-09-24 11:03:06 +02:00
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default n
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2009-10-18 20:35:50 +02:00
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help
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This option is used to enable certain functions to make coreboot
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work correctly on symmetric multi processor (SMP) systems.
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2009-10-02 01:22:50 +02:00
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2012-02-14 09:39:17 +01:00
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config AP_SIPI_VECTOR
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hex
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default 0xfffff000
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help
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This must equal address of ap_sipi_vector from bootblock build.
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2012-03-31 13:08:12 +02:00
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2009-10-02 01:22:50 +02:00
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config MMX
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bool
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2010-02-25 14:40:49 +01:00
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help
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Select MMX in your socket or model Kconfig if your CPU has MMX
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streaming SIMD instructions. ROMCC can build more efficient
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code if it can spill to MMX registers.
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2009-10-02 01:22:50 +02:00
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config SSE
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bool
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2010-02-25 14:40:49 +01:00
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help
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Select SSE in your socket or model Kconfig if your CPU has SSE
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streaming SIMD instructions. ROMCC can build more efficient
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code if it can spill to SSE (aka XMM) registers.
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config SSE2
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bool
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2010-03-19 03:33:40 +01:00
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default n
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2017-06-16 22:20:57 +02:00
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select SSE
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2010-02-25 14:40:49 +01:00
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help
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Select SSE2 in your socket or model Kconfig if your CPU has SSE2
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streaming SIMD instructions. Some parts of coreboot can be built
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with more efficient code if SSE2 instructions are available.
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2009-10-06 22:48:07 +02:00
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2012-07-20 07:11:21 +02:00
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endif # ARCH_X86
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2013-12-05 05:21:15 +01:00
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config SUPPORT_CPU_UCODE_IN_CBFS
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2012-07-20 07:11:21 +02:00
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bool
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2012-07-11 02:02:21 +02:00
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default n
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2012-07-20 07:11:21 +02:00
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2015-11-05 16:03:45 +01:00
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config USES_MICROCODE_HEADER_FILES
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def_bool n
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select SUPPORT_CPU_UCODE_IN_CBFS
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help
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This is selected by a board or chipset to set the default for the
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microcode source choice to a list of external microcode headers
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2012-07-20 07:11:21 +02:00
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choice
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2013-02-27 20:24:11 +01:00
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prompt "Include CPU microcode in CBFS" if ARCH_X86
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2015-11-05 16:03:45 +01:00
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default CPU_MICROCODE_CBFS_EXTERNAL_HEADER if USES_MICROCODE_HEADER_FILES
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2015-03-07 09:15:02 +01:00
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default CPU_MICROCODE_CBFS_GENERATE if SUPPORT_CPU_UCODE_IN_CBFS && USE_BLOBS
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2013-12-05 05:21:15 +01:00
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default CPU_MICROCODE_CBFS_NONE if !SUPPORT_CPU_UCODE_IN_CBFS
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2012-07-20 07:11:21 +02:00
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config CPU_MICROCODE_CBFS_GENERATE
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bool "Generate from tree"
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2012-06-19 06:20:20 +02:00
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help
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2012-07-20 07:11:21 +02:00
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Select this option if you want microcode updates to be assembled when
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building coreboot and included in the final image as a separate CBFS
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file. Microcode will not be hard-coded into ramstage.
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2012-06-19 06:20:20 +02:00
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2013-04-01 13:45:44 +02:00
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The microcode file may be removed from the ROM image at a later
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2012-07-20 07:11:21 +02:00
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time with cbfstool, if desired.
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If unsure, select this option.
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2015-11-05 16:03:45 +01:00
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config CPU_MICROCODE_CBFS_EXTERNAL_HEADER
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bool "Include external microcode header files"
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help
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Select this option if you want to include external c header files
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containing the CPU microcode. This will be included as a separate
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file in CBFS.
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A word of caution: only select this option if you are sure the
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microcode that you have is newer than the microcode shipping with
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coreboot.
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The microcode file may be removed from the ROM image at a later
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time with cbfstool, if desired.
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If unsure, select "Generate from tree"
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2012-07-20 07:11:21 +02:00
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config CPU_MICROCODE_CBFS_NONE
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bool "Do not include microcode updates"
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help
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Select this option if you do not want CPU microcode included in CBFS.
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Note that for some CPUs, the microcode is hard-coded into the source
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tree and is not loaded from CBFS. In this case, microcode will still
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be updated. There is a push to move all microcode to CBFS, but this
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change is not implemented for all CPUs.
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This option currently applies to:
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- Intel SandyBridge/IvyBridge
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- VIA Nano
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Microcode may be added to the ROM image at a later time with cbfstool,
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if desired.
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If unsure, select "Generate from tree"
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The GOOD:
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Microcode updates intend to solve issues that have been discovered
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after CPU production. The expected effect is that systems work as
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intended with the updated microcode, but we have also seen cases where
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issues were solved by not applying microcode updates.
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The BAD:
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Note that some operating system include these same microcode patches,
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so you may need to also disable microcode updates in your operating
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system for this option to have an effect.
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The UGLY:
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A word of CAUTION: some CPUs depend on microcode updates to function
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correctly. Not updating the microcode may leave the CPU operating at
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less than optimal performance, or may cause outright hangups.
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There are CPUs where coreboot cannot properly initialize the CPU
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without microcode updates
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For example, if running with the factory microcode, some Intel
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SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
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will hang when changing the frequency.
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Make sure you have a way of flashing the ROM externally before
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selecting this option.
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endchoice
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2013-02-18 17:26:01 +01:00
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2015-10-08 23:58:58 +02:00
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config CPU_MICROCODE_MULTIPLE_FILES
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bool
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default n
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depends on CPU_MICROCODE_CBFS_GENERATE
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help
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Select this option to install separate microcode container files into
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CBFS instead of using the traditional monolithic microcode file format.
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2015-11-05 16:03:45 +01:00
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config CPU_MICROCODE_HEADER_FILES
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string "List of space separated microcode header files with the path"
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depends on CPU_MICROCODE_CBFS_EXTERNAL_HEADER
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help
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A list of one or more microcode header files with path from the
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coreboot directory. These should be separated by spaces.
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2016-08-31 00:21:53 +02:00
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config CPU_UCODE_BINARIES
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string "Microcode binary path and filename"
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depends on CPU_MICROCODE_CBFS_GENERATE
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default ""
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help
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Some platforms have microcode in the blobs directory, and these can
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be hardcoded in the makefiles. For platforms with microcode
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binaries that aren't in the makefile, set this option to pull
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in the microcode.
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This should contain the full path of the file for one or more
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microcode binary files to include, separated by spaces.
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If unsure, leave this blank.
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