2012-10-30 15:03:43 +01:00
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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# Run an intermediate step when producing coreboot.rom
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# that adds additional components to the final firmware
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# image outside of CBFS
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# FIXME, uncomment as soon as we have ME firmware in the blobs repo
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# INTERMEDIATE:=lynxpoint_add_me
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ramstage-y += pch.c
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ramstage-y += azalia.c
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ramstage-y += lpc.c
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ramstage-y += pci.c
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ramstage-y += pcie.c
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ramstage-y += sata.c
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ramstage-y += usb_ehci.c
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2013-05-30 00:27:55 +02:00
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ramstage-y += usb_xhci.c
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2012-10-30 15:03:43 +01:00
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ramstage-y += me_9.x.c
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ramstage-y += smbus.c
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2013-06-20 21:40:55 +02:00
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ramstage-y += hda_verb.c
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2013-03-22 19:21:14 +01:00
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ramstage-$(CONFIG_INTEL_LYNXPOINT_LP) += serialio.c
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2012-10-30 15:03:43 +01:00
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2013-02-15 22:52:28 +01:00
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ramstage-y += rcba.c
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2012-10-30 15:03:43 +01:00
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ramstage-y += me_status.c
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ramstage-y += reset.c
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ramstage-y += watchdog.c
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ramstage-y += acpi.c
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lynxpoint: Add cbfs_load_payload() implementation
SPI accesses can be slow depending on the setup and the access pattern.
The current SPI hardware setup to cache and prefetch. The alternative
cbfs_load_payload() function takes advantage of the caching in the CPU
because the ROM is cached as write protected as well as the SPI's
hardware's caching/prefetching implementation. The CPU will fetch
consecutive aligned cachelines which will hit the ROM as
cacheline-aligned addresses. Once the payload is mirrored into RAM the
segment loading can take place by reading RAM instead of ROM.
With the alternative cbfs_load_payload() the boot time on a baskingridge
board saves ~100ms. This savings is observed using cbmem.py after
performing warm reboots and looking at TS_SELFBOOT_JUMP (99) entries.
This is booting with a depthcharge payload whose payload file fits
within the SMM_DEFAULT_SIZE (0x10000 bytes).
Datapoints with TS_LOAD_PAYLOAD (90) & TS_SELFBOOT_JUMP (99) cbmem entries:
Baseline Alt
-------- --------
90:3,859,310 (473) 90:3,863,647 (454)
99:3,989,578 (130,268) 99:3,888,709 (25,062)
90:3,899,450 (477) 90:3,860,926 (463)
99:4,029,459 (130,008) 99:3,890,583 (29,657)
90:3,834,600 (466) 90:3,890,564 (465)
99:3,964,535 (129,934) 99:3,920,213 (29,649)
Booted baskingridge many times and observed 100ms reduction in
TS_SELFBOOT_JUMP times (time to load payload).
Change-Id: I27b2dec59ecd469a4906b4179b39928e9201db81
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2783
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-22 20:54:12 +01:00
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ramstage-$(CONFIG_ALT_CBFS_LOAD_PAYLOAD) += spi_loading.c
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2012-10-30 15:03:43 +01:00
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ramstage-$(CONFIG_ELOG) += elog.c
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ramstage-y += spi.c
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smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
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2013-03-09 01:01:44 +01:00
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c pmutil.c
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2013-05-01 20:30:24 +02:00
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c finalize.c pch.c
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2013-03-09 01:01:44 +01:00
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smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c
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2012-10-30 15:03:43 +01:00
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2012-12-19 18:31:17 +01:00
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romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c
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2013-02-15 22:52:28 +01:00
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romstage-y += reset.c early_spi.c rcba.c
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2012-10-30 15:03:43 +01:00
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2012-12-17 20:29:10 +01:00
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ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
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romstage-y += lp_gpio.c
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ramstage-y += lp_gpio.c
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2013-07-04 02:55:38 +02:00
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smm-$(CONFIG_HAVE_SMI_HANDLER) += lp_gpio.c
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2012-12-17 20:29:10 +01:00
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else
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romstage-y += gpio.c
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ramstage-y += gpio.c
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2013-07-04 02:55:38 +02:00
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smm-$(CONFIG_HAVE_SMI_HANDLER) += gpio.c
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2012-12-17 20:29:10 +01:00
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endif
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2012-10-30 15:03:43 +01:00
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lynxpoint_add_me: $(obj)/coreboot.pre $(IFDTOOL)
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printf " DD Adding Intel Firmware Descriptor\n"
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2013-06-13 15:07:02 +02:00
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dd if=$(CONFIG_IFD_BIN_PATH) \
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2012-10-30 15:03:43 +01:00
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of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
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printf " IFDTOOL me.bin -> coreboot.pre\n"
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$(objutil)/ifdtool/ifdtool \
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2013-06-13 15:07:02 +02:00
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-i ME:$(CONFIG_ME_BIN_PATH) \
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2012-10-30 15:03:43 +01:00
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$(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
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printf " IFDTOOL Locking Management Engine\n"
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$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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else
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printf " IFDTOOL Unlocking Management Engine\n"
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$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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endif
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PHONY += lynxpoint_add_me
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