2020-05-08 19:28:13 +02:00
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/* inteltool - dump all registers on an Intel CPU + chipset based system */
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2017-04-05 17:39:57 +02:00
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <inttypes.h>
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#include <assert.h>
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#include "pcr.h"
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const uint8_t *sbbar = NULL;
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uint32_t read_pcr32(const uint8_t port, const uint16_t offset)
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{
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assert(sbbar);
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return *(const uint32_t *)(sbbar + (port << 16) + offset);
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}
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2018-03-13 21:58:52 +01:00
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static void print_pcr_port(const uint8_t port)
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{
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size_t i = 0;
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uint32_t last_reg = 0;
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bool last_printed = true;
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printf("PCR port offset: 0x%06zx\n\n", (size_t)port << 16);
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for (i = 0; i < PCR_PORT_SIZE; i += 4) {
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const uint32_t reg = read_pcr32(port, i);
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const bool rep = i && last_reg == reg;
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if (!rep) {
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if (!last_printed)
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printf("*\n");
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printf("0x%04zx: 0x%08"PRIx32"\n", i, reg);
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}
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last_reg = reg;
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last_printed = !rep;
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}
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if (!last_printed)
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printf("*\n");
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}
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void print_pcr_ports(struct pci_dev *const sb,
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const uint8_t *const ports, const size_t count)
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{
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size_t i;
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pcr_init(sb);
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for (i = 0; i < count; ++i) {
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printf("\n========== PCR 0x%02x ==========\n\n", ports[i]);
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print_pcr_port(ports[i]);
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}
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}
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2017-04-05 17:39:57 +02:00
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void pcr_init(struct pci_dev *const sb)
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{
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bool error_exit = false;
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bool p2sb_revealed = false;
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2018-11-20 12:10:29 +01:00
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struct pci_dev *p2sb;
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2019-02-19 11:51:34 +01:00
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bool use_p2sb = true;
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pciaddr_t sbbar_phys;
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2017-04-05 17:39:57 +02:00
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if (sbbar)
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return;
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2018-11-20 12:10:29 +01:00
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switch (sb->device_id) {
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE:
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2019-02-19 23:49:11 +01:00
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_PRE:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_SKL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_SKL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_SKL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE_KBL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM_KBL:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM_KBL:
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2019-01-02 06:45:16 +01:00
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
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case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
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2018-11-20 12:10:29 +01:00
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case PCI_DEVICE_ID_INTEL_H110:
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case PCI_DEVICE_ID_INTEL_H170:
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case PCI_DEVICE_ID_INTEL_Z170:
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case PCI_DEVICE_ID_INTEL_Q170:
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case PCI_DEVICE_ID_INTEL_Q150:
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case PCI_DEVICE_ID_INTEL_B150:
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case PCI_DEVICE_ID_INTEL_C236:
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case PCI_DEVICE_ID_INTEL_C232:
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case PCI_DEVICE_ID_INTEL_QM170:
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case PCI_DEVICE_ID_INTEL_HM170:
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case PCI_DEVICE_ID_INTEL_CM236:
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case PCI_DEVICE_ID_INTEL_HM175:
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case PCI_DEVICE_ID_INTEL_QM175:
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case PCI_DEVICE_ID_INTEL_CM238:
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2019-08-17 13:54:02 +02:00
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case PCI_DEVICE_ID_INTEL_C621:
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case PCI_DEVICE_ID_INTEL_C622:
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case PCI_DEVICE_ID_INTEL_C624:
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case PCI_DEVICE_ID_INTEL_C625:
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case PCI_DEVICE_ID_INTEL_C626:
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case PCI_DEVICE_ID_INTEL_C627:
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case PCI_DEVICE_ID_INTEL_C628:
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case PCI_DEVICE_ID_INTEL_C629:
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case PCI_DEVICE_ID_INTEL_C624_SUPER:
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case PCI_DEVICE_ID_INTEL_C627_SUPER_1:
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case PCI_DEVICE_ID_INTEL_C621_SUPER:
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case PCI_DEVICE_ID_INTEL_C627_SUPER_2:
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case PCI_DEVICE_ID_INTEL_C628_SUPER:
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2019-01-12 19:20:50 +01:00
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case PCI_DEVICE_ID_INTEL_DNV_LPC:
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2018-11-20 12:10:29 +01:00
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p2sb = pci_get_dev(sb->access, 0, 0, 0x1f, 1);
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break;
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case PCI_DEVICE_ID_INTEL_APL_LPC:
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p2sb = pci_get_dev(sb->access, 0, 0, 0x0d, 0);
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break;
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2019-02-19 11:51:34 +01:00
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case PCI_DEVICE_ID_INTEL_H310:
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case PCI_DEVICE_ID_INTEL_H370:
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case PCI_DEVICE_ID_INTEL_Z390:
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case PCI_DEVICE_ID_INTEL_Q370:
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case PCI_DEVICE_ID_INTEL_B360:
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case PCI_DEVICE_ID_INTEL_C246:
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case PCI_DEVICE_ID_INTEL_C242:
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case PCI_DEVICE_ID_INTEL_QM370:
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case PCI_DEVICE_ID_INTEL_HM370:
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case PCI_DEVICE_ID_INTEL_CM246:
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2019-06-12 06:23:46 +02:00
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case PCI_DEVICE_ID_INTEL_CANNONPOINT_LP_U_PREM:
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2020-01-04 15:14:59 +01:00
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case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U:
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2019-02-19 11:51:34 +01:00
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sbbar_phys = 0xfd000000;
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use_p2sb = false;
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break;
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2018-11-20 12:10:29 +01:00
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default:
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perror("Unknown LPC device.");
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exit(1);
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}
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2017-04-05 17:39:57 +02:00
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2019-02-19 11:51:34 +01:00
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if (use_p2sb) {
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if (!p2sb) {
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perror("Can't allocate device node for P2SB.");
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2017-04-05 17:39:57 +02:00
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exit(1);
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}
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2019-02-19 11:51:34 +01:00
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/* do not fill bases here, libpci refuses to refill later */
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pci_fill_info(p2sb, PCI_FILL_IDENT);
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if (p2sb->vendor_id == 0xffff && p2sb->device_id == 0xffff) {
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printf("Trying to reveal Primary to Sideband Bridge "
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"(P2SB),\nlet's hope the OS doesn't mind... ");
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/* Do not use pci_write_long(). Bytes
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surrounding 0xe0 must be maintained. */
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pci_write_byte(p2sb, 0xe0 + 1, 0);
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pci_fill_info(p2sb, PCI_FILL_IDENT | PCI_FILL_RESCAN);
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if (p2sb->vendor_id != 0xffff ||
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p2sb->device_id != 0xffff) {
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printf("done.\n");
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p2sb_revealed = true;
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} else {
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printf("failed.\n");
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exit(1);
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}
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}
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pci_fill_info(p2sb, PCI_FILL_BASES | PCI_FILL_CLASS);
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sbbar_phys = p2sb->base_addr[0] & ~0xfULL;
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2017-04-05 17:39:57 +02:00
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}
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printf("SBREG_BAR = 0x%08"PRIx64" (MEM)\n\n", (uint64_t)sbbar_phys);
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sbbar = map_physical(sbbar_phys, SBBAR_SIZE);
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if (sbbar == NULL) {
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perror("Error mapping SBREG_BAR");
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error_exit = true;
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}
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2019-02-19 11:51:34 +01:00
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if (use_p2sb) {
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if (p2sb_revealed) {
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printf("Hiding Primary to Sideband Bridge (P2SB).\n");
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pci_write_byte(p2sb, 0xe0 + 1, 1);
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}
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pci_free_dev(p2sb);
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2017-04-05 17:39:57 +02:00
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}
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if (error_exit)
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exit(1);
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}
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void pcr_cleanup(void)
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{
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if (sbbar)
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unmap_physical((void *)sbbar, SBBAR_SIZE);
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}
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