GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
coreboot-kgpe-d16/src/soc/amd/stoneyridge/northbridge.c

559 lines
16 KiB
C
Raw Normal View History

soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015-2016 Advanced Micro Devices, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <arch/acpi.h>
#include <arch/acpigen.h>
#include <cbmem.h>
#include <chip.h>
#include <console/console.h>
#include <cpu/amd/mtrr.h>
soc/amd/stoneyridge: don't open code known literals We have macros for register addresses. Use it for MMIO_CONF_BASE instead of duplicating a literal again. Change-Id: I2250ea990bafa234fd5fea48d2690edcfc4982b9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-03 19:14:25 +01:00
#include <cpu/amd/amdfam15.h>
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
#include <cpu/cpu.h>
amd/stoneyridge: Remove fixme.c Move the two functions in fixme.c to places where they make more sense. Coincidentally fix the todo in amd_initcpuio() and use bsp_topmem() instead of explicitely reading the MSR. BUG=b:62241048 Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-02 16:49:30 +01:00
#include <cpu/x86/lapic_def.h>
amd/stoneyridge: Clean up include files in northbridge.h Add an extra include file to northbridge.c for completeness. cpu/msr.h is already included in cpu/amd/mtrr.h which allows the file to build properly. Remove include files that are no longer required for the file. Change-Id: I3e5ab39fd0640d2983fc5b7b202fb65d42c5ce3d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21615 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-21 02:01:41 +02:00
#include <cpu/x86/msr.h>
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
soc/amd/common: Move Agesa related headers Move AGESA related headers in soc/amd/common to soc/amd/common/block/include/amdblocks. BUG=b:69262110 TEST=Build with no error gardenia and kahlee (no code change, headers moved). Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22772 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-12-09 00:53:29 +01:00
#include <amdblocks/agesawrapper.h>
#include <amdblocks/agesawrapper_call.h>
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
#include <soc/northbridge.h>
amd/stoneyridge: Remove fixme.c Move the two functions in fixme.c to places where they make more sense. Coincidentally fix the todo in amd_initcpuio() and use bsp_topmem() instead of explicitely reading the MSR. BUG=b:62241048 Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-02 16:49:30 +01:00
#include <soc/southbridge.h>
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
#include <soc/pci_devs.h>
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
typedef struct dram_base_mask {
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
u32 base; /* [47:27] at [28:8] */
u32 mask; /* [47:27] at [28:8] and enable at bit 0 */
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
} dram_base_mask_t;
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
static dram_base_mask_t get_dram_base_mask(void)
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
{
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
device_t dev = dev_find_slot(0, ADDR_DEVFN);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
dram_base_mask_t d;
u32 temp;
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
/* [39:24] at [31:16] */
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
temp = pci_read_config32(dev, 0x44);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
/* mask out DramMask [26:24] too */
d.mask = ((temp & 0xfff80000) >> (8 + 3));
/* [47:40] at [7:0] */
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
temp = pci_read_config32(dev, 0x144) & 0xff;
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
d.mask |= temp << 21;
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
temp = pci_read_config32(dev, 0x40);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
d.mask |= (temp & 1); /* enable bit */
d.base = ((temp & 0xfff80000) >> (8 + 3));
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
temp = pci_read_config32(dev, 0x140) & 0xff;
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
d.base |= temp << 21;
return d;
}
static void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 io_min, u32 io_max)
{
u32 tempreg;
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
device_t addr_map = dev_find_slot(0, ADDR_DEVFN);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
/* io range allocation. Limit */
tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4)
| ((io_max & 0xf0) << (12 - 4));
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
pci_write_config32(addr_map, reg + 4, tempreg);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
pci_write_config32(addr_map, reg, tempreg);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
}
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index,
u32 mmio_min, u32 mmio_max)
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
{
u32 tempreg;
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
device_t addr_map = dev_find_slot(0, ADDR_DEVFN);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
/* io range allocation. Limit */
tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00);
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
pci_write_config32(addr_map, reg + 4, tempreg);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00);
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
pci_write_config32(addr_map, reg, tempreg);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
}
static void read_resources(device_t dev)
{
/*
* This MMCONF resource must be reserved in the PCI domain.
* It is not honored by the coreboot resource allocator if it is in
* the CPU_CLUSTER.
*/
soc/amd/stoneyridge: don't open code known literals We have macros for register addresses. Use it for MMIO_CONF_BASE instead of duplicating a literal again. Change-Id: I2250ea990bafa234fd5fea48d2690edcfc4982b9 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-03 19:14:25 +01:00
mmconf_resource(dev, MMIO_CONF_BASE);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
}
static void set_resource(device_t dev, struct resource *resource, u32 nodeid)
{
resource_t rbase, rend;
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
unsigned int reg, link_num;
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
char buf[50];
/* Make certain the resource has actually been set */
if (!(resource->flags & IORESOURCE_ASSIGNED))
return;
/* If I have already stored this resource don't worry about it */
if (resource->flags & IORESOURCE_STORED)
return;
/* Only handle PCI memory and IO resources */
if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
return;
/* Ensure I am actually looking at a resource of function 1 */
if ((resource->index & 0xffff) < 0x1000)
return;
/* Get the base address */
rbase = resource->base;
/* Get the limit (rounded up) */
rend = resource_end(resource);
/* Get the register and link */
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
reg = resource->index & 0xfff; /* 4k */
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
link_num = IOINDEX_LINK(resource->index);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
if (resource->flags & IORESOURCE_IO)
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
else if (resource->flags & IORESOURCE_MEM)
set_mmio_addr_reg(nodeid, link_num, reg,
(resource->index >> 24), rbase >> 8, rend >> 8);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
resource->flags |= IORESOURCE_STORED;
snprintf(buf, sizeof(buf), " <node %x link %x>",
nodeid, link_num);
report_resource_stored(dev, resource, buf);
}
/**
* I tried to reuse the resource allocation code in set_resource()
* but it is too difficult to deal with the resource allocation magic.
*/
static void create_vga_resource(device_t dev)
{
struct bus *link;
/* find out which link the VGA card is connected,
* we only deal with the 'first' vga card */
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
for (link = dev->link_list ; link ; link = link->next)
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
break;
/* no VGA card installed */
if (link == NULL)
return;
amd/stoneyridge: Simplify SB link routing Remove the check for the southbridge link from Stoney Ridge. The APU is an SoC which can never be installed in a multi-node system. It is pointless to detect and remember the sblink value, which is set by hardware and comes up 0. The BKDG marks this as a reserved field vs. documentation for multi-node-capable Family 15h devices. Because there is only one option for SB link now, relocate the register write done by set_vga_enable_reg() and remove the function. Change-Id: Ie4ce6b5aa847a184534224db302437ff8d37c14b Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 18:46:36 +02:00
printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev));
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
/* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */
pci_write_config32(dev_find_slot(0, ADDR_DEVFN), 0xf4, 1);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
}
static void set_resources(device_t dev)
{
struct bus *bus;
struct resource *res;
/* do we need this? */
create_vga_resource(dev);
/* Set each resource we have found */
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
for (res = dev->resource_list ; res ; res = res->next)
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
set_resource(dev, res, 0);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
for (bus = dev->link_list ; bus ; bus = bus->next)
if (bus->children)
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
assign_resources(bus);
}
static void northbridge_init(struct device *dev)
{
}
static unsigned long acpi_fill_hest(acpi_hest_t *hest)
{
void *addr, *current;
/* Skip the HEST header. */
current = (void *)(hest + 1);
addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
if (addr != NULL)
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
current += acpi_create_hest_error_source(hest, current, 0,
(void *)((u32)addr + 2), *(UINT16 *)addr - 2);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
if (addr != NULL)
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
current += acpi_create_hest_error_source(hest, current, 1,
(void *)((u32)addr + 2), *(UINT16 *)addr - 2);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
return (unsigned long)current;
}
static void northbridge_fill_ssdt_generator(device_t device)
{
msr_t msr;
char pscope[] = "\\_SB.PCI0";
acpigen_write_scope(pscope);
msr = rdmsr(TOP_MEM);
acpigen_write_name_dword("TOM1", msr.lo);
msr = rdmsr(TOP_MEM2);
/*
* Since XP only implements parts of ACPI 2.0, we can't use a qword
* here.
* See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
* slide 22ff.
* Shift value right by 20 bit to make it fit into 32bit,
* giving us 1MB granularity and a limit of almost 4Exabyte of memory.
*/
acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
acpigen_pop_len();
}
static unsigned long agesa_write_acpi_tables(device_t device,
unsigned long current,
acpi_rsdp_t *rsdp)
{
acpi_srat_t *srat;
acpi_slit_t *slit;
acpi_header_t *ssdt;
acpi_header_t *alib;
acpi_header_t *ivrs;
acpi_hest_t *hest;
/* HEST */
current = ALIGN(current, 8);
hest = (acpi_hest_t *)current;
acpi_write_hest((void *)current, acpi_fill_hest);
acpi_add_table(rsdp, (void *)current);
current += ((acpi_header_t *)current)->length;
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current);
ivrs = agesawrapper_getlateinitptr(PICK_IVRS);
if (ivrs != NULL) {
memcpy((void *)current, ivrs, ivrs->length);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
ivrs = (acpi_header_t *)current;
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
current += ivrs->length;
acpi_add_table(rsdp, ivrs);
} else {
printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n");
}
/* SRAT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
if (srat != NULL) {
memcpy((void *)current, srat, srat->header.length);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
srat = (acpi_srat_t *)current;
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
current += srat->header.length;
acpi_add_table(rsdp, srat);
} else {
printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n");
}
/* SLIT */
current = ALIGN(current, 8);
printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
if (slit != NULL) {
memcpy((void *)current, slit, slit->header.length);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
slit = (acpi_slit_t *)current;
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
current += slit->header.length;
acpi_add_table(rsdp, slit);
} else {
printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n");
}
/* ALIB */
current = ALIGN(current, 16);
printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
if (alib != NULL) {
memcpy((void *)current, alib, alib->length);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
alib = (acpi_header_t *)current;
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
current += alib->length;
acpi_add_table(rsdp, (void *)alib);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
} else {
printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL."
" Skipping.\n");
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
}
current = ALIGN(current, 16);
printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
if (ssdt != NULL) {
memcpy((void *)current, ssdt, ssdt->length);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
ssdt = (acpi_header_t *)current;
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
current += ssdt->length;
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
} else {
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n");
}
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
acpi_add_table(rsdp, ssdt);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current);
return current;
}
static struct device_operations northbridge_operations = {
.read_resources = read_resources,
.set_resources = set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
.acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator,
.write_acpi_tables = agesa_write_acpi_tables,
.enable = 0,
.ops_pci = 0,
};
static const struct pci_driver family15_northbridge __pci_driver = {
.ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT,
};
amd/stoneyridge: Remove fixme.c Move the two functions in fixme.c to places where they make more sense. Coincidentally fix the todo in amd_initcpuio() and use bsp_topmem() instead of explicitely reading the MSR. BUG=b:62241048 Change-Id: Ica80b92f48788314ad290ccf72e6847fb6d039c3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-02 16:49:30 +01:00
/*
* Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET,
* BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining
* MMIO to posted. Route all I/O to the southbridge.
*/
void amd_initcpuio(void)
{
uintptr_t topmem = bsp_topmem();
uintptr_t base, limit;
/* Enable legacy video routing: D18F1xF4 VGA Enable */
pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE);
/* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */
base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE;
limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP;
pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit);
pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base);
/* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */
base = (topmem >> 8) | MMIO_WE | MMIO_RE;
limit = ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8;
pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(1), limit);
pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(1), base);
/* Route all I/O downstream */
base = 0 | IO_WE | IO_RE;
limit = ALIGN_DOWN(0xffff, 4 * KiB);
pci_write_config32(SOC_ADDR_DEV, NB_IO_LIMIT(0), limit);
pci_write_config32(SOC_ADDR_DEV, NB_IO_BASE(0), base);
}
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
void fam15_finalize(void *chip_info)
{
device_t dev;
u32 value;
soc/amd/stoneyridge: Use macros for PCI_DEVFN calls * Change all calls to PCI_DEVFN to macros * Remove CBB and CDB Kconfig since these are static for stoneyridge BUG=b:62200746 TEST=build Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-19 19:45:30 +02:00
dev = dev_find_slot(0, GNB_DEVFN); /* clear IoapicSbFeatureEn */
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
pci_write_config32(dev, 0xf8, 0);
pci_write_config32(dev, 0xfc, 5); /* TODO: move it to dsdt.asl */
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
/* disable No Snoop */
soc/amd/stoneyridge: Use macros for PCI_DEVFN calls * Change all calls to PCI_DEVFN to macros * Remove CBB and CDB Kconfig since these are static for stoneyridge BUG=b:62200746 TEST=build Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-19 19:45:30 +02:00
dev = dev_find_slot(0, HDA0_DEVFN);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
value = pci_read_config32(dev, 0x60);
value &= ~(1 << 11);
pci_write_config32(dev, 0x60, value);
}
void domain_read_resources(device_t dev)
{
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
unsigned int reg;
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
device_t addr_map = dev_find_slot(0, ADDR_DEVFN);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
/* Find the already assigned resource pairs */
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
for (reg = 0x80 ; reg <= 0xd8 ; reg += 0x08) {
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
u32 base, limit;
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
base = pci_read_config32(addr_map, reg);
limit = pci_read_config32(addr_map, reg + 4);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
/* Is this register allocated? */
if ((base & 3) != 0) {
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
unsigned int nodeid, reg_link;
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
device_t reg_dev = dev_find_slot(0, HT_DEVFN);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
if (reg < 0xc0) /* mmio */
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
nodeid = (limit & 0xf) + (base & 0x30);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
else /* io */
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
nodeid = (limit & 0xf) + ((base >> 4) & 0x30);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
reg_link = (limit >> 4) & 7;
if (reg_dev) {
/* Reserve the resource */
struct resource *res;
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
res = new_resource(reg_dev,
IOINDEX(0x1000 + reg,
reg_link));
if (res)
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
res->flags = 1;
}
}
}
/* FIXME: do we need to check extend conf space?
I don't believe that much preset value */
pci_domain_read_resources(dev);
}
void domain_enable_resources(device_t dev)
{
if (acpi_is_wakeup_s3())
soc/amd/common: Update agesawrapper_call.h Solve issues related to agesawrapper_call.h that came up at review 75dd50e233 (review 19724). This includes a hard coded table size and 2 macros: AGESAWRAPPER_PRE_CONSOLE() and AGESAWRAPPER(). Remove AGESAWRAPPER_PRE_CONSOLE(), and replace AGESAWRAPPER() calls with the actual content of the macro. BUG=b:62240989 TEST=Build kahlee with no errors, boot recording serial output and compare to serial output from a build without these changes. Change-Id: Ic51917d3961a51d4e725ff45b04f45eefe149855 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22850 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-13 21:26:21 +01:00
do_agesawrapper(agesawrapper_fchs3laterestore,
"fchs3laterestore");
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
/* Must be called after PCI enumeration and resource allocation */
soc/amd/common: Update agesawrapper_call.h Solve issues related to agesawrapper_call.h that came up at review 75dd50e233 (review 19724). This includes a hard coded table size and 2 macros: AGESAWRAPPER_PRE_CONSOLE() and AGESAWRAPPER(). Remove AGESAWRAPPER_PRE_CONSOLE(), and replace AGESAWRAPPER() calls with the actual content of the macro. BUG=b:62240989 TEST=Build kahlee with no errors, boot recording serial output and compare to serial output from a build without these changes. Change-Id: Ic51917d3961a51d4e725ff45b04f45eefe149855 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22850 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-12-13 21:26:21 +01:00
else
do_agesawrapper(agesawrapper_amdinitmid, "amdinitmid");
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n");
}
void domain_set_resources(device_t dev)
{
unsigned long mmio_basek;
u32 pci_tolm;
amd/stoneyridge: Simplify memory hole calculation Delete the obselete Kconfig symbols regarding the memory hole. Integrate the hole check into domain_set_resources(). The hardware configuration is done by AGESA, so only discover the setting and adjust the mmio_basek accordingly. BUG=b:66202887 TEST=Check settings with HDT Change-Id: Id15a88897e29bff28ab7c498dc4d3818834f08b2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 22:59:45 +02:00
u32 hole;
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
int idx;
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
struct bus *link;
amd/stoneyridge: Enable SMM in TSEG Add necessary features to allow mp_init_with_smm() to install and relocate an SMM handler. SMM region functions are added to easily identify the SMM attributes. Adjust the neighboring cbmem_top() rounding downward to better reflect the default TSEG size. Add relocation attributes to be set by each core a relocation handler. Modify the definition of smi_southbridge_handler() to match TSEG prototype. BUG=b:62103112 Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-14 01:47:31 +02:00
void *tseg_base;
size_t tseg_size;
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
pci_tolm = 0xffffffffUL;
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
for (link = dev->link_list ; link ; link = link->next)
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
pci_tolm = find_pci_tolm(link);
amd/stoneyridge: Simplify memory hole calculation Delete the obselete Kconfig symbols regarding the memory hole. Integrate the hole check into domain_set_resources(). The hardware configuration is done by AGESA, so only discover the setting and adjust the mmio_basek accordingly. BUG=b:66202887 TEST=Check settings with HDT Change-Id: Id15a88897e29bff28ab7c498dc4d3818834f08b2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 22:59:45 +02:00
/* Start with alignment supportable in variable MTRR */
mmio_basek = ALIGN_DOWN(pci_tolm, 4 * KiB) / KiB;
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
amd/stoneyridge: Simplify memory hole calculation Delete the obselete Kconfig symbols regarding the memory hole. Integrate the hole check into domain_set_resources(). The hardware configuration is done by AGESA, so only discover the setting and adjust the mmio_basek accordingly. BUG=b:66202887 TEST=Check settings with HDT Change-Id: Id15a88897e29bff28ab7c498dc4d3818834f08b2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21496 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06 22:59:45 +02:00
/*
* AGESA may have programmed the memory hole and rounded down to a
* 128MB boundary. If we find it's valid, adjust mmio_basek downward
* to the hole bottom. D18F1xF0[DramHoleBase] is granular to 16MB.
*/
hole = pci_read_config32(dev_find_slot(0, ADDR_DEVFN), D18F1_DRAM_HOLE);
if (hole & DRAM_HOLE_VALID)
mmio_basek = min(mmio_basek, ALIGN_DOWN(hole, 16 * MiB) / KiB);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
idx = 0x10;
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
dram_base_mask_t d;
resource_t basek, limitk, sizek; /* 4 1T */
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
d = get_dram_base_mask();
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
if ((d.mask & 1)) { /* if enabled... */
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
/* could overflow, we may lose 6 bit here */
basek = ((resource_t)(d.base & 0x1fffff00)) << 9;
limitk = ((resource_t)(((d.mask & ~1) + 0x000ff)
& 0x1fffff00)) << 9;
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
sizek = limitk - basek;
/* see if we need a hole from 0xa0000 to 0xbffff */
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
if ((basek < ((8 * 64) + (8 * 16))) && (sizek > ((8 * 64) +
(16 * 16)))) {
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
ram_resource(dev, idx, basek,
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
((8 * 64) + (8 * 16)) - basek);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
idx += 0x10;
basek = (8 * 64) + (16 * 16);
sizek = limitk - ((8 * 64) + (16 * 16));
}
/* split the region to accommodate pci memory space */
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
if ((basek < 4 * 1024 * 1024) && (limitk > mmio_basek)) {
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
if (basek <= mmio_basek) {
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
unsigned int pre_sizek;
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
pre_sizek = mmio_basek - basek;
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
if (pre_sizek > 0) {
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
ram_resource(dev, idx, basek,
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
pre_sizek);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
idx += 0x10;
sizek -= pre_sizek;
}
basek = mmio_basek;
}
if ((basek + sizek) <= 4 * 1024 * 1024) {
sizek = 0;
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
} else {
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
uint64_t topmem2 = bsp_topmem2();
basek = 4 * 1024 * 1024;
sizek = topmem2 / 1024 - basek;
}
}
amd/stoneyridge: Remove multi-node support The Stoney Ridge APU can never be used in a multi-node system. Reduce the feature set to a single node. Remove the static variables for each D18Fn device and replace the routines with coreboot config read and write functions. Strip down domain_set_resources() to consider only a single node. A follow-on patch will further simplify this. Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-01 17:54:48 +02:00
ram_resource(dev, idx, basek, sizek);
printk(BIOS_DEBUG, "node 0: mmio_basek=%08lx, basek=%08llx,"
" limitk=%08llx\n", mmio_basek, basek, limitk);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
}
amd/stoneyridge: Make UMA memory cacheable Use reserved_ram_resource to help ensure the UMA memory is typed as WB. BUG=b:65856868 TEST=Inspect MTRRs and compare with UMA memory Change-Id: Ifa54d9b1c206d2ee6dc4b8f90b445a6820ceb8fd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21606 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-20 00:26:34 +02:00
/* UMA is not set up yet, but infer the base & size to make cacheable */
uint32_t uma_base = restore_top_of_low_cacheable();
if (uma_base != bsp_topmem()) {
uint32_t uma_size = bsp_topmem() - uma_base;
printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n",
__func__, uma_size, uma_base);
reserved_ram_resource(dev, 7, uma_base / KiB, uma_size / KiB);
}
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
for (link = dev->link_list ; link ; link = link->next)
if (link->children)
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
assign_resources(link);
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
/*
* Reserve everything between A segment and 1MB:
*
* 0xa0000 - 0xbffff: legacy VGA
* 0xc0000 - 0xfffff: RAM
*/
mmio_resource(dev, 0xa0000, 0xa0000 / KiB, 0x20000 / KiB);
reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB);
amd/stoneyridge: Enable SMM in TSEG Add necessary features to allow mp_init_with_smm() to install and relocate an SMM handler. SMM region functions are added to easily identify the SMM attributes. Adjust the neighboring cbmem_top() rounding downward to better reflect the default TSEG size. Add relocation attributes to be set by each core a relocation handler. Modify the definition of smi_southbridge_handler() to match TSEG prototype. BUG=b:62103112 Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-14 01:47:31 +02:00
/* Reserve TSEG */
smm_region_info(&tseg_base, &tseg_size);
idx += 0x10;
reserved_ram_resource(dev, idx, (unsigned long)tseg_base/KiB,
tseg_size/KiB);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
}
/*********************************************************************
* Change the vendor / device IDs to match the generic VBIOS header. *
*********************************************************************/
u32 map_oprom_vendev(u32 vendev)
{
u32 new_vendev;
new_vendev =
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) ?
0x100298e0 : vendev;
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
if (vendev != new_vendev)
soc/amd/stoneyridge: Fix most checkpatch errors Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-15 20:17:38 +02:00
printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n",
vendev, new_vendev);
soc/amd/stoneyridge: Add northbridge support Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-05-16 02:55:11 +02:00
return new_vendev;
}
Reference in a new issue Copy permalink