soc/amd/*/acpi: add comment about p_lvl[2,3]_lat FADT field usage

The latency values in the _CST package override the values in the
p_lvl2_lat and p_lvl3_lat FADT fields. In Picasso, Cezanne, Mendocino,
Phoenix and Glinda generate_cpu_entries generates the _CST packages for
each CPU device. The coreboot code for Stoneyridge doesn't generate _CST
packages for the CPU objects, but those are provided via the PSTATE SSDT
binaryPI generates and agesa_write_acpi_tables gets and adds to the ACPI
tables. The AGESA reference code also sets those two FADT entries to the
equivalents of ACPI_FADT_C2_NOT_SUPPORTED and ACPI_FADT_C3_NOT_SUPPORTED
so this also matches the AGESA behavior.

From the ACPI 6.4 spec: "Values provided by the _CST object override
P_LVLx values in P_BLK and P_LVLx_LAT values in the FADT."

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1116a3013576b18b6f521604d6b0a9d75b971e0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>

src/soc/amd/cezanne/acpi.c

@@ -76,6 +76,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	fill_fadt_extended_pm_regs(fadt);
 
+	/* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
+	   overridden by the _CST packages in the processor devices. */
 	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
 	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
 	fadt->duty_offset = 0;	/* Not supported */

src/soc/amd/glinda/acpi.c

@@ -79,6 +79,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	fill_fadt_extended_pm_regs(fadt);
 
+	/* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
+	   overridden by the _CST packages in the processor devices. */
 	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
 	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
 	fadt->duty_offset = 0;	/* Not supported */

src/soc/amd/mendocino/acpi.c

@@ -78,6 +78,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	fill_fadt_extended_pm_regs(fadt);
 
+	/* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
+	   overridden by the _CST packages in the processor devices. */
 	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
 	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
 	fadt->duty_offset = 0;	/* Not supported */

src/soc/amd/phoenix/acpi.c

@@ -79,6 +79,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	fill_fadt_extended_pm_regs(fadt);
 
+	/* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
+	   overridden by the _CST packages in the processor devices. */
 	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
 	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
 	fadt->duty_offset = 0;	/* Not supported */

src/soc/amd/picasso/acpi.c

@@ -82,6 +82,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	fill_fadt_extended_pm_regs(fadt);
 
+	/* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
+	   overridden by the _CST packages in the processor devices. */
 	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
 	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
 	fadt->duty_offset = 1;	/* CLK_VAL bits 3:1 */

src/soc/amd/stoneyridge/acpi.c

@@ -74,6 +74,8 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 
 	fill_fadt_extended_pm_regs(fadt);
 
+	/* p_lvl2_lat and p_lvl3_lat match what the AGESA code does, but those values are
+	   overridden by the _CST packages in the PSTATE SSDT. */
 	fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
 	fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
 	fadt->duty_offset = 1;	/* CLK_VAL bits 3:1 */