Adds TIANOCORE_FOLLOW_BGRT_SPEC which, when enabled, will follow
the BGRT Specification implemented by Microsoft and the Boot Logo
will be vertically centered 38.2% from the top of the display.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If508166fe657d1cc032dd09a0fa231c7b60d9846
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add TIANOCORE_BOOT_MANAGER_ESCAPE which, when enabled, will use
Escape as the hot-key to access the Boot Manager. This replaces
the default key of F2.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1e60d116367542f55f0ffa241a6132e4faabe446
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some processor families allow for SMM setup to be done in parallel.
On processors that have this feature, the BIOS resource list becomes
unusable for some processors during STM startup.
This patch covers two cases: (1) The BIOS resource list becomes twice
as long because the smm_relocation function is called twice - this is
resolved by recreating the list on each invocation. (2) Not all
processors receive the correct resource list pointer - this is resolved
by having every processor execute the pointer calculation code, which is
a lot faster then forcing all processors to spin lock waiting for this
value to be calculated.
This patch has been tested on a Purism L1UM-1X8C and Purism 15v4.
Signed-off-by: Eugene Myers <cedarhouse@comcast.net>
Change-Id: I7619038edc78f306bd7eb95844bd1598766f8b37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Commit ea3376c (SMM module loader version 2) changedhow the
SMBASE is calculated.
This patch modifies setup_smm_descriptor to properly acquire the
SMBASE.
This patch has been tested on a Purism L1UM-1X8C and a Purism 15v4.
Signed-off-by: Eugene Myers <cedarhouse@comcast.net>
Change-Id: I1d62a36cdcbc20a19c42266164e612fb96f91953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61688
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit b433d26ef1 (arch/x86: Define
HPET_ADDRESS_OVERRIDE) added this Kconfig option and referenced the
via/cx700 chipset which has been dropped before the 4.9 release. No SoC
in the current tree selects HPET_ADDRESS_OVERRIDE and all SoCs have
their HPET mapped at 0xfed00000, so drop this unused and no longer
needed Kconfig option.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4021ed6f84473c7a9223323fc8aa5d3f935d8084
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62276
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The AMD SoCs had a check to make sure that HPET_ADDRESS_OVERRIDE isn't
set so that the HPET_ADDRESS Kconfig option will have the right default
value. Instead check if the HPET_ADDRESS Kconfig value matches the
HPET_BASE_ADDRESS define in the SoC code which is the case if
HPET_ADDRESS_OVERRIDE isn't selected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icf1832eb36c031e93ba24f342e9a8a7bf13faecc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62275
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To be able to link libcbfs without vboot, we need garbage
collection now.
Change-Id: Id9a9fe7efb9fb4409a43ae8357f4f683618805d2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Casts from integer to pointer are usually a case for phys_to_virt().
Change-Id: I861d435ff2361cdc26a2abd46d43b9346fa67ccc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Turns out 200ms still isn't enough in the worst reset conditions.
There's been some reports of failures at 200ms with some older
cr50 versions. Let's not take any chances and bump this way up
since if this fails, it prevents boot.
BUG=b:213828947
BRANCH=None
TEST=Reboot and suspend_stress on Nipperkin
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I5be0a80c064546fd277f66135abc9d0572df11cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The ddr_base_info struct, which stores basic DDR information, should be
platform independent. Currently the struct is defined in each SoC's
dramc_parah.h. To prevent code duplication, move it as well as other
related structs and enums to a common header.
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I99772427f9b0755dc2c778b5f4150b2f8147bcc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
VSRAM_CORE is not used on kingler/krabby, so we disable it.
This implementation is according to chapter 3.7 in MT8186 Functional
Specification.
BUG=b:220071688
TEST=the rail steadily shows 0V in either S0, S3, and S5.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5256f6a2c0ca5a951dc79f564575b526a84463fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62253
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since commit 7cd8ba6eda (console: Add loglevel prefix to interactive
consoles) on the very first boot some errors occur because no MRC data
is present in the MRC cache. This is normal because the memory training
is not done yet.
This patch changes the loglevel to BIOS_NOTICE which will prevent an
error in the log in this case.
Change-Id: I1e36590e33507515e5b9dd4eb361b3dbe165511e
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61973
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the LOG_FAST macro, the comparison was incorrectly made with 'level'
value. Correct is the comparison with 'speed'.
With the wrong comparison you cannot set a lower level for console log,
the highest level is always output.
TEST:
- Boot mc_ehl2 with console log level 5 and check output
Change-Id: Ib5b4537ae2cbf01c51c3568d312b5242c4bee7bb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
While on it, use tab for indent.
Change-Id: I6cb0b4183db819d721f4882ab2168d22bcd664e3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reconfigure the GPIO's so that they are configured correctly.
The original configuration was based on the AMI firmware, and
whilst it worked, it wasn't optimal.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I27ecf066685f2a81ac884a9f276c518544449443
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reconfigure the CNVi GPIO's so that they are configured correctly.
The original configuration was based on the AMI firmware, and
whilst it worked, it wasn't optimal.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9fc9963e91da0267c8740fee20a3ec41895b4953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Update trackpad GPIO to avoid IRQ Storm, that causes high power
consumption when idling or in S3.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ieee27bd9079617ab95f4f1e27ef98b49e89e5b41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Configure the TPM IRQ GPIO for TGL (StarBook Mk V) so that the
hardware TPM can be used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ife88075e70184b46e69f2e24c70b85ec254edd64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60756
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't configure ESPI GPIOs as the default values are correct.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I052fbfccd075d19340d3e27ad0c62965c80badaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth - Personal <martinroth@google.com>
Rework edkii makefile so that the various build options are
unified between CorebootPayloadPkg, uefipayload_202107 and
upstream.
This sets the project directory based on the git repository name
i.e. https://github.com/mrchromebox/edk2 becomes mrchomebox
Also builds to $(obj)/UEFIPAYLOAD.fd and allows using a commit
ID without a branch.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth - Personal <martinroth@google.com>
The SoC-specific I2C code and header file have been verified some time
ago, but it seems that I forgot to remove the corresponding TODOs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifd162bda10e5993bc32db3a77588491397e3c19e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
CPUID_ALDERLAKE_N_A0 is ES. Add it to generate is_es = 1 in ACPI
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: Icc65c52a9dadebe4ebab3d0c30599eb0db38bc3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Using __fallthrough instead of a comment about the fall-through being
intentional should make clang stop complaining about intended fall-
through statements.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I940529be02e20c72f6e97b2cfa10f0dd8f7020b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Compiling vboot_check.c depends on fmap_config.h already being generated
so add this dependency.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1fe2b738d76ae16dee3e1ebdca512264303a481c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
On mc_apl2 the external RTC is connected to I2C bus 3. All other I2C bus
devices (16.0, 16.1 and 16.2) have been disabled as they are not used.
While coreboot can handle the case where a PCI device does not have
function 0 enabled but a later one (here function 3), Linux seems to
check for function 0 first and ignores the rest if function 0
is missing. So enable PCI device 16.0 in order to let Linux use 16.3
again.
Test=Boot into Linux and make sure that PCI device 16.0 and 16.3 are
visible and I2C attached RTC works properly.
Change-Id: I55a748b6de8128f4b26b908118feff9f06d3fb7c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Modify function to set default audio codec HID
to be original setting 10EC5682.
BUG=b:204517112
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ic37e7e6757476f1d30bea31fcde4deebebd488a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Modify function to set default audio codec HID
to be original setting 10EC5682.
BUG=b:204523176
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I36e35522aba2463124b7e6e7046b1a56758b534d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Modify function to set default audio codec HID
to be original setting 10EC5682.
BUG=b:218245715
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I30a1fe2ef8d750616f6907f86a5329f035920504
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: Ie9dbed7d6dd1e5f0c97d4a6cedea3d6bd7b000a2
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Change-Id: I69c4b3cdd2473655064d1329d5319cffdba2425a
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
The rom layout for A/B recovery:
EFS -> PSP L1 0x48 -> PSP L2 A -> BIOS L2 A
0x4A -> PSP L2 B -> BIOS L2 B
The coreboot doesn't implement the AMD's A/B recovery. This is only
for the ROM layout. To save some flash space, the entire B section can
be eliminated.
To enable A/B recovery in PSP layout, add "--recovery-ab" to
amdfwtool.
TEST=Majolica(Cezanne)
Change-Id: I27f5d3476f648fcecafb8d258ccb6cfad4f50036
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add the information of substance and instance in the string for PMUI
and PMUD. It is amdfwtool's job to extract the number from the string.
Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Based on the nivviks and nereid schematics, nissa is using eMMC HS400
mode, so enable this in devicetree.
BUG=b:197479026
TEST=Build test nivviks and nereid
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ie9772385276d3629079b95024d3ffa04438f22c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Sean Rhodes