Commit Graph

46869 Commits

Author SHA1 Message Date
Felix Held 02512eeb2e soc/amd/common/block/i2c/i23c_pad_def.h: fix off by one in define
I23C_PAD_CTRL_SLEW_N_SHIFT is 6 and not 7 which matches both with the
PPR #57243 revision 1.53 and with I23C_PAD_CTRL_SLEW_N_MASK which covers
both bits 6 and 7.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I622717bebaffe34b6df5e578b082dc10e2a98256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63216
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01 14:30:50 +00:00
Varshit B Pandya d025ab3bc2 soc/intel/alderlake: Add HID for DPTF Power Participant
BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check TPWR device HID

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I82507a3c0a521adbb8dec5520fd6d2ea3782c60e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-01 13:45:57 +00:00
Varshit B Pandya e7d3a1a9e8 drivers/intel/dptf: Add support for Power participant
As per Intel Dynamic Tuning revision 1.3.13 (Doc no: 541817)
Add support for TPWR device under \_SB.DPTF

BUG=b:205928013
TEST=Build, boot brya0 and dump SSDT to check TPWR device

Device (TPWR)
{
    Name (_HID, "INTC1060")  // _HID: Hardware ID
    Name (_UID, "TPWR")  // _UID: Unique ID
    Name (_STR, "Power Participant")  // _STR: Description String
    Name (PTYP, 0x11)
    Method (_STA, 0, NotSerialized)  // _STA: Status
    {
        Return (0x0F)
    }
}

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62944
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01 13:45:49 +00:00
Alan Huang 47b7904d78 mb/google/brya/variants/baseboard/brask: Turn off NFC power in S0ix
Turn off the NFC power which is controlled by GPP_D3 to save power in
S0ix states. For an USB device, the S0ix hook is needed for the on/off
operations to take place.

BUG=b:202737385
BRANCH=firmware-brya-14505.B
TEST=measure the voltage of GPP_D3 in S0ix states

Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I69588c82dfde1744c45c7aff3ac05b80bb16a8f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-04-01 13:45:38 +00:00
Arthur Heymans 0c6298761b arch/x86/Kconfig: Drop obsolete fixed ramstage symbols
On x86 ramstage is always relocated at runtime in cbmem so there is no
need to have this configurable in Kconfig.

Change-Id: I01b2335d0b82bea8f885ee5ca9814351bbf2aa3c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63215
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01 13:45:07 +00:00
Casper Chang 32a1d7ea8c mb/google/brya/var/primus{4es}: Decrease touchscreen T3 timing to 200ms
We set T3 as 300ms to meet Elan's spec, but the resume/suspend times
are greater than 500ms, which is the spec for Chromebooks.
The actual kernel timing has been measured, and given the ACPI delay
after deasserting reset in addition to the delay until the kernel
driver accesses the device, delaying only 200ms in the ACPI method is
also sufficient to meet the 300ms requirement.

BUG=b:223936777
BRANCH=none
TEST=build and test touchscreen function on DUT.
TEST=suspend, wake DUT and check touchscreen function.

Change-Id: I6b04cf6392d924aed01ca36b720f889b88d92311
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-04-01 13:45:00 +00:00
Reka Norman 390c3f2b47 mb/google/brya/var/nereid: Enable AUX DC biasing on C0 and C1
C0 has no redriver, so enable SBU muxing in the SoC.

C1 has a redriver which does SBU muxing, so disable SBU muxing in the
SoC. However, this also disables AUX biasing when the pins are
configured as NF6. So instead configure the C1 AUX bias pins as GPO.

BUG=b:227259673
TEST=Voltages are correct on the C0 and C1 AUX bias pins

Change-Id: Ic0af662ecc1c6cee15b4ae98cb02deeefc93a71e
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
2022-04-01 13:44:52 +00:00
Arthur Heymans 56ed0bee86 drivers/intel/fsp1_1: Reduce scope of functions
Reduce scope of get_next_hob and drop unused functions.

Change-Id: I81007295ed2d1592c4d829cbb277c0726d89ea4b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-04-01 13:44:46 +00:00
Michael Niewöhner 10e47d80cb mb/clevo/tgl-u: add new board L14xMU
Add new board Clevo L14xMU (TGL).

GPIOs were configured based on schematics.

Tested and working:
 - On-board RAM (M471A1G44AB0-CWE)
 - DIMM slot (tested Crucial CT16G4SFD8266.16FJ1 / MTA16ATF2G64HZ-2G6J1)
 - Graphics (GOP driver), including HDMI
 - Keyboard
 - I2C touchpad (including interrupt)
 - TPM (with interrupt on Windows, only polling on Linux [1])
 - microSD Card reader
 - both NVME ports
 - Speakers
 - Microphone
 - Camera
 - WLAN/BT (CNVi)
 - All USB2/3 ports including Type-C
 - Thunderbolt detects my work laptop in TB Control Center
   (I couldn't test anything more due to security policy.)
 - TianoCore
 - internal flashing with flashrom on vendor firmware

Note on TPM:
The vendor sets Intel PTT to default-on in newer CSME images, which
conflicts with the dTPM. Currently, there are two ways to make it work:

 1) Boot vendor firmware once to let it disable PTT via CSME firmware
    feature override.
 2) Use Intel Flash Image Tool (FIT) to set "initial power-up state" to
    disabled.

Boots fine:
 - Debian testing, unstable (Linux 5.16.14, 5.17.0-rc6)
 - Windows 10 21H2 (Build 19044.1586)

Untested:
- Thunderbolt (see above)
- Type-C DisplayPort
- S-ATA

Doesn't work:
 - TPM interrupt on Linux [1]
 - All EC related functions - EC driver is WIP
  - WLAN/BT (PCIe) - gets detected but can't be enabled
  - 3G/LTE (not powered without EC driver)
  - Fn-Keys
  - S0ix
  - UCSI
  - Fan control
  - Battery info

[1] https://lkml.org/lkml/2021/5/1/103

Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-04-01 12:20:33 +00:00
Arthur Heymans 422fdceaa8 cpu/intel/fit: Clear the FIT table when setting pointer
When rebuilding coreboot the empty fit table added to added to CBFS
stays the same so the build process sees no reason to update the file.
In the meantime ifittool did update that file for instance to add
microcode update entries. So each time coreboot is rebuilt the entries
are appended to the FIT table which runs out of space at some point.
One way to deal with this is to clear the fit table when setting the
pointer inside the bootblock.

TESTED: Now running 'make' again on prodrive/hermes does not report an
error with a filled FIT table.

Change-Id: Ia20a489dc90a4ae704e9ee6d532766899f83ffcc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63036
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01 09:29:24 +00:00
Arthur Heymans 8b82c6b91b util/ifittool: Fix clearing FIT when setting the pointer
When setting the FIT pointer, the FIT table is only known later in the
codeflow.

Change-Id: I658f4fffa997d1f7beaf6d6ae37d2885ae602e5c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63035
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-04-01 09:29:19 +00:00
Shelley Chen dd6b0610e3 soc/qualcomm/common: Increase SPI gpios drive strength to 8mA
EE requested that we increase the drive strength for the SPI lines to
8mA.

BUG=b:198627043
BRANCH=None
TEST=EE help verify

Change-Id: Ic887a7eef74f1063f7284db042c5fbd2e1d5bd4c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-04-01 01:20:58 +00:00
Jakub Czapiga 48f6c2b46f util/cbmem: Add FlameGraph-compatible timestamps output
Flame graphs are used to visualize hierarchical data, like call stacks.
Timestamps collected by coreboot can be processed to resemble
profiler-like output, and thus can be feed to flame graph generation
tools.

Generating flame graph using https://github.com/brendangregg/FlameGraph:
  cbmem -S > trace.txt
  FlameGraph/flamegraph.pl --flamechart trace.txt > output.svg

TEST=Run on coreboot-enabled device and extract timestamps using
     -t/-T/-S options

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I3a4e20a267e9e0fbc6b3a4d6a2409b32ce8fca33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-31 23:04:58 +00:00
Arthur Heymans f91366fa6f Makefile: Clean up old targets
Some of these targets seem to come from a long time ago. Now just
rm -rf $(obj) is all that is needed for a clean.

Change-Id: Iccc62b3c54ee2a074c25674715403c1457f6aad3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
2022-03-31 17:37:59 +00:00
Tony Huang f00ab8c26a mb/google/brya/var/agah: Replace amp max98390 with max98360
Based on the latest schematic, agah will replace the Maxim 98390
speaker amps with Maxim max98360. This patch updates the
devicetree entries to reflect that.

BUG=b:210970640
BRANCH=brya
TEST=emerge-draco coreboot

Change-Id: I7ea36d276f7ffeae1510483027092e2bc59690fc
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-31 15:03:36 +00:00
Tony Huang bcfc87dbff mb/google/brya/var/agah: Add GL9750 SD card reader support
BUG=b:210970640
TEST=emerge-draco coreboot

Change-Id: I881c2c1ad7b0d10b7ae38fcd9814f757cf56feb5
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-31 15:03:04 +00:00
Dtrain Hsu 67f32c0365 mb/google/brya/var/kinox: set GPP_D0 to NC
Brask set GPP_D0 to GPO in commit b0769db4, but Kinox doesn't support
fingerprint. This patch sets GPP_D0 to NC for matching schematic.

BUG=b:214025396
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I38b9eb2df83cfbdb58d95cb178c1d767299aa4da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-03-31 15:00:00 +00:00
John 7cd968e69b soc/intel/common: Add Kconfig SOC_INTEL_CSE_SET_EOP
The do_send_end_of_post function is implemented in the cse_eop.c file.
This change adds the Kconfig SOC_INTEL_CSE_SET_EOP in cse.c to avoid
build issue.

Change-Id: Ib52404d9ad4c01a460e4cfef331c529d2a53337a
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2022-03-31 14:22:21 +00:00
Patrick Rudolph ac49aaf0f9 drivers/intel/fsp1_1: Fix code not working with strict-aliasing rules
Change-Id: Ifc95a093cf86c834d63825bf76312ed21ec68215
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-31 14:21:27 +00:00
Patrick Rudolph d7803c89b6 vendorcode/intel: Remove UDK2015 headers
The headers are now unused, drop them.

Change-Id: Ibfaa3029ddc614935481ce736c9d971bf4831b5d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-31 14:21:06 +00:00
Patrick Rudolph 05ca05466c Kconfig: Select UDK2017
On platforms using UDK2015 select UDK2017 instead.
This allows to drop UDK2015 headers.

Tested using timeless builds: The produced binaries are identical.

Change-Id: Ia6032c6520ec889cd63655db982d9bfa476dc24d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-31 14:20:44 +00:00
Patrick Rudolph dcf30e837b soc/intel/denverton_ns: Resolve macro conflicts with UDK2017 headers
Replace LShiftU64 and RShiftU64 as the defined macro conflicts with
UDK2017 headers.

Tested using timeless builds: The produced binaries are identical.

Change-Id: I8f205f663be9c9c31cf384ca89370afa48ca1e15
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2022-03-31 14:20:22 +00:00
Jianjun Wang 79b35ca481 soc/mediatek/early_init: Fix function return type
Fix return type of early_init_get_elapsed_time_us() to comply with the
data type of return value.

Also replace memset() with struct initializer.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Fixes: commit 41faa22 (soc/mediatek: Add early_init for passing data
       across stages)
Change-Id: I7c361828362c2dfec91358ad8a420f5360243da0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-03-31 01:50:42 +00:00
David Wu e1e30b1504 mb/google/brya/var/kano: Remove SAR sensor
RF team comfirmed that SAR sensor is not necessary for MP,
therefore remove the corresponding entries from the devicetree.

BUG=b:202978964
TEST=Build pass.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I31faf18563848f8d6787fe70bfb28006efea8427
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 23:57:43 +00:00
Terry Chen 239d7d0e5d mb/google/brya/variants/crota: Add memory config for crota
Fill in the memory config based on the the schematic by bernadino 14 adl-p 20220112.pdf

BUG=b:219891328

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I981d2cd6feafee8c10ec9724a3dec9a23ba0ddd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 23:55:46 +00:00
David Wu ad2e4eaf7a Revert "mb/google/brya/var/kano: adjust I2C3 speed"
This reverts commit 65aaccda59.
Reason:
1. Fix firmware messages show [ERROR] dw_i2c:invalid bus speed 390000
2. Measure DVT I2C3 speed < 400KHz.

BUG=b:215095284
TEST=There isn't ERROR messages and verify I2C3 speed < 400KHz.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I5982c82a55710824692b41e263418e4b4d420b02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 23:55:30 +00:00
Sridhar Siricilla abe0d810f0 soc/intel/alderlake: Log CSE RO write protection info for ADL
The patch logs CSE RO's write protection information for Alder Lake
platform. As part of write protection information, coreboot logs status
on CSE RO write protection and range. Also, logs error message if EOM
is disabled, and write protection for CSE RO is not enabled.

TEST=Verify the write protection details on Gimble.

Excerpt from Gimble coreboot log:
	[DEBUG]  ME: WP for RO is enabled        : YES
	[DEBUG]  ME: RO write protection scope - Start=0x1000, End=0x15AFFF

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 23:55:15 +00:00
Felix Held e3ee917cba soc/amd/sabrina/makefile: use Sabrina as SoC name in amdfwtool call
Now that the amdfwtool support for Sabrina is in place, change the
SoC name parameter passed to amdfwtool from Cezanne to Sabrina.

The fw.cfg file still points to the Cezanne binaries, but since
commit 9cb0a05dfb (soc/amd/sabrina: Add
prompt for AMDFW_CONFIG_FILE) this can be overridden via the Kconfig
config file in the build. As soon as the Sabrina PSP binaries are
available in 3rparty/amd_blobs, the fw.cfg file will be updated to use
the correct ones for Sabrina.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53a8de222e39bd2b92c07661b6c52a02fb651609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63189
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 23:42:39 +00:00
Felix Held dd031ffee8 soc/amd/sabrina/makefile: drop PSP_S0I3_RESUME_VERSTAGE handling
The PSP_S0I3_RESUME_VERSTAGE Kconfig symbol is only defined in the
Cezanne Kconfig, so drop this from the Sabrina makefile.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9571a302d427981cdf750a1cb3b7f4db9d61a87c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63188
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 23:42:28 +00:00
Felix Held f8e2e47e2b util/amdfwtool: use ISH support for Sabrina SoC
The PSP in the Sabrina SoC uses the image slot header to find the second
level PSP directory table, so it needs the ISH to be generated.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9e6308854147c9f6f72d722215c833ee86ee4f94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63186
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 23:42:14 +00:00
Felix Held b18a4c7d0d util/amdfwtool: add Sabrina SoC type
Add PLATFORM_SABRINA to the enum of supported platforms and integrate it
into the existing code.

Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibe52b44395619f697686bd900a522562abbe7646
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-30 23:41:53 +00:00
Felix Held 830add6e27 util/amdfwtool: select A/B recovery when ISH is used
In newer AMD SoCs, the image slot header is used in the AMD A/B recovery
scheme, so set recovery_ab to true when need_ish is true. Also move the
block of code before the process_config call, since that call will
already use the recovery_ab field of the cb_config struct.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I65903765514f215bf5cc9b949d0b95aff781eb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63184
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 23:41:48 +00:00
Raul E Rangel 879a2789ee mb/google/skyrim: Call espi_switch_to_spi1_pads
We are using the second SPI pads for eSPI.

BUG=b:226635441
TEST=Build skyrim

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I43713d7376a28ced2be635668836464ceec46392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63096
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 22:42:01 +00:00
Raul E Rangel d0b059fcd4 soc/amd/sabrina: Add espi_switch_to_spi1_pads
The way to select the pads has changed from Cezanne.

BUG=b:226635441
TEST=Build skyrim

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I96baf6b9c169ed61d221352b29ac676bca40da21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63095
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-03-30 22:41:53 +00:00
Felix Held 21a8e381ea util/amdfwtool: use table-relative addressing in ISH case
When the image slot header (ISH) is used, the addresses in the PSP and
BIOS directory tables need to be relative to the beginning of the table.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia61f7c8313d5a1af95c68b9177a53a2f5443552a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-30 22:20:04 +00:00
Kyösti Mälkki 1d8c7da5b4 ChromeoS: Retain ACPI CNVS contents on S3 resume
For platforms without EC_GOOGLE_CHROMEEC S3 resume path
always reported ACTIVE_ECFW_RO because acpi_fill_cnvs()
and mainboard_chromeos_acpi_generate() were not called.

Change-Id: Iea71a51aba7ab1b6966389c17a1e06ccc96ae0e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 21:43:00 +00:00
Chris.Wang 4a45771edf mb/google/guybrush/var/dewatt: add specific SPD hex for dewatt
Add the specific SPD hex file for the Samsung memory part with
updating the part number into the SPD table. The ABL needs to
identify the part by checking SPD data to do the proper tuning.

BUG=b:224884904
TEST=Build, validate the SPD data has been applied.

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ia54726ce8c1bae46dcd4fed3df509ef184914e94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2022-03-30 21:40:30 +00:00
Jakub Czapiga 2b3e6d6736 commonlib/timestamp_serialized: Add timestamp enum to name mapping
Some solutions require readable form of timestamps, which does not
contain spaces. Current descriptive timestamp names do not meet this
criteria. Also, mapping enums to their text representation allows for
quick grepping (use of grep command) to find relevant timestamps in the
code.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ifd49f20d6b00a5bbd21804cea3a50b8cef074cd1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-30 21:21:53 +00:00
Jakub Czapiga 9760264a96 commonlib/bsd/helpers: Remove redundancy with libpayload defines
Move STRINGIFY() from coreboot string.h to commonlib/bsd/helpers.h
Remove redundant defines from libpayload.h and libpayloads' standard
headers.

Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I3263b2aa7657759207bf6ffda750d839e741f99c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2022-03-30 21:21:47 +00:00
Idwer Vollering 70f3d43854 util/genbuild_h: micro-adjust the regexp used to set COREBOOT_MAJOR_VERSION
On FreeBSD, every build target would show warnings from its
builtin printf().
Change the regexp to be compatible with BSD sed.
This will avoid noise like "printf: 4.14-1278-g5d74ccf1c3: not
completely converted".

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Signed-off-by: Jessica Clarke <jrtc27@jrtc27.com>
Change-Id: I1c0c260fd8d42e23a612a353a288e472cc068c8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2022-03-30 20:06:57 +00:00
Terry Chen 707eaced71 mb/google/brya/variants/crota: init overridetree for crota
init overridetree.cb based on the schematic bernadino 14 adl-p 20220112.pdf

BUG=b:226315394

Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ibca9d93a81469730e472a645c607a97a624e9a1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 15:16:14 +00:00
Frank Wu ebd6dec110 mb/google/brya/var/banshee: Update the GPP_D12 as USB_C3_LSX_RX
Update the GPP_D12 according to USB_C3_LSX_RX.

BUG=b:225081954
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
The device can be recognized when it is attached in port3.
localhost /sys/bus/thunderbolt/devices # ls
0-0  1-0  1-0:3.1  1-3  domain0  domain1

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I38caa76c855e683eb0587eb67ee9abc91af4545d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-30 15:08:51 +00:00
Jianjun Wang 1c27671504 mb/google/cherry: Add PCIe domain support for dojo
Add override device tree for dojo and add PCIe domain support.

Reference:
  - MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250)

TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
 == NVME IDENTIFY CONTROLLER DATA ==
    PCI VID   : 0x15b7
    PCI SSVID : 0x15b7
    SN        : 21517J440114
    MN        : WDC PC SN530 SDBPTPZ-256G-1006
    RAB       : 0x4
    AERL      : 0x7
    SQES      : 0x66
    CQES      : 0x44
    NN        : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006

BUG=b:178565024
BRANCH=cherry

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-03-30 14:59:55 +00:00
Joey Peng 51a43f922c mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL for tarlo
Add thermal table settings for tarlo which shares the same firmware with
taeko

BUG=b:215033683
TEST=emerge-brya coreboot

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2022-03-30 14:54:49 +00:00
Yu-Hsuan Hsu 2363f0563c mb/google/guybrush: Disable EN_SPKR on init
We don't want to enable the speaker on init. It will be enabled while
using GPIO AMP codec in depthcharge.

BUG=b:223289882
TEST=boot guybrush and verify the devbeep and gpio value in kernel

Change-Id: Ic949cc95556913a2afef4a683a49eaa1e07e6147
Signed-off-by: Yu-Hsuan Hsu <yuhsuan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2022-03-30 14:26:04 +00:00
Sean Rhodes 0b158d43df mb/starlabs/lite: Move Verb Table to variant directory
Move the verb table to variant directory to allow for different tables
for different variants.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4260188057d1c3b4e6ea7c82f085fad0cc244881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30 14:23:08 +00:00
Sean Rhodes b5fbb55f0c ec/starlabs/merlin: Add GLKR variant
Add GLKR (N5030) Lite Mk IV variant

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1e17130caa16a605d0d3207d41527df3db6ada81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30 14:22:50 +00:00
Sean Rhodes 78342989c4 ec/starlabs/merlin: Add support for Nuvoton EC's
Support was created for the NPCE9m5x series, using version 1.1
of the datasheet. The specific model tested was the NPCE985P/G,
on the StarLite Mk IV with version 1.00 of the EC firmware.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib66baf1e88f5d548ce955dffa00c9b88255b2f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2022-03-30 14:22:08 +00:00
Sean Rhodes 6082ee5281 ec/starlabs/merlin: Make EC function names generic
Rather than using `ite_`, use `ec_` so the same functions
can be called for different ECs.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie61af233f731eb47772af1c82c6abdc515bc89cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30 13:49:22 +00:00
Sean Rhodes 36e2b4b2b4 ec/starlabs/merlin: Rename ec.c to more specific ite.c
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0bac5e4c101792dd4c6a0d4a1ae4a4c7fcd837d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-03-30 13:48:11 +00:00