Commit Graph

31800 Commits

Author SHA1 Message Date
Kyösti Mälkki 44f1af2996 intel/braswell: Remove duplicate set_max_freq() prototypes
Change-Id: I13ec9f477c64831848fb0e80b97bfbc10896c195
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-08 07:45:00 +00:00
Kyösti Mälkki c7fa911279 eltan/security: Replace __PRE_RAM__ with ENV_ROMSTAGE_OR_BEFORE
Change-Id: Id56a63a67b7eb70dce6687bb9c2734a711f611b3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36635
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-08 07:44:12 +00:00
Kyösti Mälkki bf43f9ef13 eltan/security: Replace __BOOTBLOCK__ with ENV_BOOTBLOCK
Change-Id: I6ec5a33cd6a6342adfe73c050e0c376bbefad96a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-08 07:43:43 +00:00
Kyösti Mälkki ed8eaab08a eltan/security: Remove some preprocessor guards
We generally let garbage-collection take care of unused functions.
While at it, move some related variable declarations in to the
header file and declare them const like they should be.

Change-Id: I7c6fa15bd45f861f13b6123ccb14c55415e42bc7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36632
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-08 07:43:09 +00:00
Kyösti Mälkki dd227a7d97 mb/facebook/fbg1701: Remove some preprocessor guards
Change-Id: Ia7289fa8337e1a93e620a52a67ca8cbdd78a66bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-08 07:41:35 +00:00
Peichao Wang 07f798d74c mb/google/hatch/var/akemi: disable unused USB port for Akemi platform
Akemi platform dosen't support WWAN device and unused USB2 port 3, 4,
5, 7, 8 and USB3 port 3, 4, 5 so close them.

BUG=None
TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec
chromeos-bootimage

Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I7eff4da77caea7d4fe46597320be134d34d78a22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-11-08 07:41:09 +00:00
Mario Scheithauer 4e074033de soc/intel/{apl,dnv,quark}: Use strip_quotes for FSP options
The commit 8fc523e3 (drivers/intel/fsp2_0: Use strip_quotes for cbfs
filenames) breaks the Siemens APL mainboards as FSP-M never returns once
it is called. The reason for this is that the -b option is missing when
adding the FSP package to cbfs via cbfstool.
This patch fixes this issue.

TEST=tested on siemens/mc_apl5

Change-Id: I48e5fa36e1ad799d09714f53a3041f73b8ec3550
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36645
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: David Guckian
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07 14:14:20 +00:00
Subrata Banik 1b1a26acdc soc/intel/icelake: Refactor pch_early_init() code
This patch keeps required pch_early_init() function like ABASE programming,
GPE and RTC init into bootblock and moves remaining functions like
TCO configuration and SMBUS init into romstage/pch.c in order to maintain
only required chipset programming for bootblock and verstage.

TEST=Able to build and boot ICL DE system.

Change-Id: I4f0914242c3215f6bf76e41c468f544361a740d8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36627
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07 14:14:11 +00:00
Wim Vervoorn 114e2e8830 lib/cbfs: Add fallback to RO region to cbfs_boot_locate
With this change cbfs_boot_locate will check the RO (COREBOOT) region if
a file can not be found in the active RW region. By doing so it is not
required to duplicate static files that are not intended to be updated
to the RW regions.

The coreboot image can still be updated by adding the file to the RW
region.

This change is intended to support VBOOT on systems with a small flash
device.

BUG=N/A
TEST=tested on facebook fbg1701

Change-Id: I81ceaf927280cef9a3f09621c796c451e9115211
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36545
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07 14:12:00 +00:00
Kyösti Mälkki 32c8de10b0 Rangeley: Fix incorrect BCLK
Not all Rangeley SKUs have a fixed 100MHz BCLK.

As per BIOS Writer's Guide, BCLK is available in MSR_FSB_FREQ 0xCD[1:0].
Using fixed BCLK was causing wrong values of core frequencies in _PSS table
for SKUs that do not have BCLK=100MHz.

Change-Id: Id8e0244fab0283b74870950cb00a95aab2a7201f
Signed-off-by: Hannah Williams <hannah.williams@dell.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35348
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07 14:08:46 +00:00
Edward O'Callaghan 3042af6256 hatch: Create puff variant
Includes:
 - gpio mappings,
 - overridetree.cb,
 - kconfig adjustments for reading spd over smbus.

V.2: Rework devicetree with comments and drop some useless gpio maps.

BUG=b:141658115
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I6449c4fcc1df702ed4f0d35afd7b0981e4c72323
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-11-07 06:24:03 +00:00
Edward O'Callaghan 881f9cb715 mainboard/google: Allow Hatch variants to read SPD data over SMBus
All Hatch variants so far embed static SPD data encoded within the
firmware image. However we wish the flexibility for romstage
implementations that allow for reading the SPD data dynamically over
SMBus. This romstage variant allows for reading the SPD data over
SMBus.

V.2: Dispence with memcpy().
V.3: Revert back to previous patch with memcpy().
V.4: Rewrite again to avoid memcpy().

BRANCH=none
BUG=b:143134702
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: I3516a46b91840a9f6d1f4cffb2553d939d79cda2
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36449
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07 06:23:55 +00:00
Kane Chen 46b125ab6b mb/google/hatch/variants/helios: Modify touchscreen power on sequence
The previous values do not affect the touchscreen function.  But, the
previous values cause the power leakage in S0ix.

from b/142368161:

1. Modify GPP_D: The specification define T1 >= 10ms. We change it to
   12ms for a safety and low impact value in our mind.  Enable pin as
   GPP_D9 is define to be AVDD in specification. Set it to 10ms to
   make it to be the final one to pull low during power off sequence .

2. Add GPP_C4: If we set stop_off_delay_ms to be 1.  The true T4 we
   got will be 300us . Set stop_off_delay_ms to be 2 . True T4 will be
   500us . So we change it to 5 to be a low impact value in our mind
   according to the true T4 value we got .

BUG=b:142368161
BRANCH=Master
TEST=emerge-hatch coreboot chromeos-bootimage
     ./util/abuild/abuild -p none -t google/hatch -x -a

Signed-off-by: YenLu Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I86c920ff1d5c0b510adde8a37f60003072d5f4e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35907
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-07 02:08:40 +00:00
Kyösti Mälkki 2d90cb1547 arch/x86: Create preprocessed __ROMCC__ bootblock source
Output file is used only as a debugging aid.

Change-Id: Iea9e1a66409659b47dfa3945c63fa1a7874de1ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-06 14:06:51 +00:00
Arthur Heymans 585786b696 drivers/intel/fsp2_0: Hide the Kconfig option to run FSP-M XIP
This is a property of the FSP, not something the user can decide.

Change-Id: I2086e67d39e88215ee0f124583b810f7df072f80
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-06 14:05:34 +00:00
Arthur Heymans 08aeda6c14 soc/intel/common: Make native and FSP-T CAR init mutually exclusive
postcar stage does not consume cpulib.c, so don't include it there.

Change-Id: Ie723412dcf09151cdbb41e357ad9c2e4f393cb47
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36168
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06 14:02:21 +00:00
Arthur Heymans 71bd7e439f drivers/intel/fsp2_0: Move Debug options to "Debugging"
Change-Id: I8e07c8186baf3d8e91b77c5afb731d26a1abfbaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-06 14:01:48 +00:00
Arthur Heymans aae81906b9 Kconfig: Organize debugging options per file extensions
Change-Id: Ia4553fb4cd95d2f1fa86eecbf382e6e6dec52b92
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36616
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06 14:01:30 +00:00
Arthur Heymans 55f01326cc util/lint/kconfig_lint: Handle glob prefix and suffix
Change-Id: I9067a95ff171d6da58583b3d4f15596b4584d937
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-11-06 14:01:00 +00:00
Xiang Wang 4e39c824e0 lib: add calculate crc byte by byte
Change-Id: I5cab1f90452b08a464ad7a2d7e75d97187452992
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-11-06 13:58:53 +00:00
Mathew King a0218958a0 mb/g/drallion: Override smbios enclosure type for drallion
Drallion can be either a clamshell or convertible depending on the
presence of the 360 sensor board. Set the smbios type 3 enclosure type
to either CONVERTIBLE or LAPTOP accordingly.

BUG=b:143701965
TEST='dmidecode -t 3'
     Type = Convertible with sensor board connected
     Type = Laptop with sensor board disconnected

Change-Id: I766e9a4b22a490bc8252670a06504437e82f72d5
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36512
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06 13:58:08 +00:00
Mathew King 51b1fc6e39 mb/g/drallion: Consolidate 360 sensor board detection
Create a single function to determine if the 360 sensor board is present
on a device.

BUG=b:143701965
TEST='emerge-drallion coreboot'

Change-Id: I4100a9fdcfe6b7134fb238cb291cb5b0af4ec169
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2019-11-06 13:58:00 +00:00
Arthur Heymans 763eeecb30 arch/riscv: Use FDT from calling argument when using FIT
Only FIT payloads provide their own FDT.

Change-Id: Id08a12ad7b72ad539e934a133acf2c4a5bcdf1f9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36599
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06 13:57:25 +00:00
Nico Huber c01d0920bb arch/riscv: Rename `stages.c` to `romstage.c`
It's only used for romstage and is incompatible to ramstages. The latter
get `cbmem_top` passed as a third argument now.

Also drop comments that don't apply to this file anymore.

Change-Id: Ibabb022860f5d141ab35922f30e856da8473b529
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-06 13:57:12 +00:00
Arthur Heymans 214661e00c security/vboot/Kconfig: Remove unused symbols
Change-Id: I417a2ff45b4a8f5bc800459a64f1c5a861fcd3d5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2019-11-06 13:57:02 +00:00
Patrick Rudolph f8251b9860 mb/emulation/qemu: Add VBOOT support
Add VBOOT support for testing purposes.
Add a 16 MiB FMAP containing RO + RW_A.

Tested on qemu.

Change-Id: I4039d77de44ade68c7bc1f8b4b0aa21387c50f8a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-11-06 13:56:49 +00:00
Edward O'Callaghan b4741616ea mainboard/google: Rework Hatch so that SPD in CBFS is optional
All Hatch variants so far embed static SPD data encoded within the
firmware image. However we wish the flexibility for romstage
implementations that allow for reading the SPD data dynamically over
SMBus.

BRANCH=none
BUG=b:143134702
TEST=./util/abuild/abuild -p none -t google/hatch -x -a

Change-Id: Ie1637d08cdd85bc8d7c3b6f2d6f386d0e0c6589b
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-06 10:15:10 +00:00
Subrata Banik fb2a9d5ed8 soc/intel/icelake: Set FSP_TEMP_RAM_STACK unconditionally
Icelake default selects PLATFORM_USES_FSP2_1 which means stack will be shared
between FSP and coreboot (CONFIG_FSP_USES_CB_STACK) hence no need to have any
other guard to assign FSP_TEMP_RAM_SIZE.

Change-Id: Idbe393f7a63ad10f1ad3c9e7248593cf8eb115d9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36628
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-06 04:53:58 +00:00
Sumeet Pawnikar 6a657c2646 mb/google/hatch/variants/helios: Update TSR3 sensor thresholds
Update thermal threshold settings for TSR3 sensor. There is an issue
fan is always running, even during system idle state. This change
fixes this issue and fan starts only when it breaches the temperature
threshold.

BRANCH=None
BUG=b:143861559
TEST=Built and tested on Helios system

Change-Id: Ia417f8c51442005cc8c2251c188cebc197e0a773
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36609
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05 19:14:44 +00:00
Elyes HAOUAS 007af4251f superio/*/*/acpi: Improve the readability of the IndexField
Change-Id: I64fdcbcbbd54334c1c551bc1346c6000ea82c97d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-05 16:08:55 +00:00
Nico Huber ef63c32b58 arch/riscv: Don't link `stages.c` into ramstage
It's superseded by `ramstage.S`.

Change-Id: I81648da2f2af3ad73b3b51471c6fa2daac0540b1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36610
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05 15:24:15 +00:00
Ravi Sarawadi 6b5bf407de soc/intel/common: Include Tigerlake device IDs
Add Tigerlake specific CPU, System Agent, PCH, IGD device IDs.

BUG=None
BRANCH=None
TEST=Build 'emerge-tglrvp coreboot'

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I19047354718bdf510dffee4659d885f1313a751b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2019-11-05 15:05:22 +00:00
Wim Vervoorn 8fc523e313 drivers/intel/fsp2_0: Use strip_quotes for cbfs filenames
The quotes were not stripped for the cbfs filenames of the FSP
components. This is causing problems when the regions-for-file macro is
executed (when VBOOT is enabled and the files should be filtered).

BUG=N/A
TEST=build

Change-Id: I14267502cfab5308d3874a0c0fd18a71b08bb9f8
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36548
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05 15:04:54 +00:00
Wim Vervoorn 1058dd84f0 security/vboot: Removed vboot_prepare from vboot_locator
When prog_locate() is called in the stage VBOOT is starting from and the
image to be loaded is not the target image vboot_prepare() may be called
too early.

To prevent this vboot_prepare() is removed from the vboot_locator
structure. This allows more control over the start of the vboot logic.

To clarify the change the vboot_prepare() has been renamed to
vboot_run_logic() and calls to initialize vboot have been added at the
following places:

postcar_loader: when VBOOT starts in ROMSTAGE
romstage_loader: when VBOOT starts in BOOTBLOCK
ramstage_loader: when VBOOT starts in ROMSTAGE

BUG=N/A
TEST=tested on facebook fbg1701

Change-Id: Id5e8fd78458c09dd3896bfd142bd49c2c3d686df
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36543
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05 15:03:44 +00:00
Wim Vervoorn 397ce3c45f vendorcode/eltan/security: Align mboot with coreboot tpm
Align the eltan mboot support with coreboot tpm support to limit the amount of custom code.

We now only support SHA256 pcrs, only single a single digest will be handled in a call.
The pcr invalidation has been changed fixed values are now loaded while the correct algortihm is
selected.

BUG=N/A
TEST=tested on fbg1701

Change-Id: Id11389ca90c1e6121293353402a2dd464a2e6727
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2019-11-05 15:01:37 +00:00
Alex James 8119841ec0 commonlib: Use __builtin_offsetof with supported compilers
Use __builtin_offsetof (which is treated as a constant expression) with
Clang & GCC. This also allows check_member to work with Clang 9.

Signed-off-by: Alex James <theracermaster@gmail.com>
Change-Id: I8b5cb4110c13ee42114ecf65932d7f1e5636210e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36249
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05 15:00:44 +00:00
Andrey Petrov ddcfcb8ebc soc/intel/fsp_broadwell_de: Add CONFIG_IED_SIZE, drop CONFIG_SMM_TSEG_SIZE
Fix regression introduced in recent SMM region handling overhaul.
Previously IED region size was hardcoded in the code. However when
chip code was modified to use smm_region() and friends, IED_SIZE
define was not added and build system quetly substituted it with 0.

Also, drop CONFIG_SMM_TSEG_SIZE which is now obsolete.

TEST=tested on watson platform; without the patch tg3 NIC driver doesn't work
properly and that gets solved with this patch

Change-Id: Id6fb258e555bb507851886b0e75f1f53c3762276
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36417
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05 14:59:59 +00:00
Arthur Heymans 15fcc86907 pci_mmio_cfg.h: Add a compile time error if MMCONF_BASE_ADDRESS is undefined
if CONFIG_MMCONF_SUPPORT is set, add a compiletime error if
CONFIG_MMCONF_BASE_ADDRESS is not defined.

Change-Id: I0439e994d170e8ec564ce188e82a850e2a286a66
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35883
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05 14:58:58 +00:00
Elyes HAOUAS 92a7599616 src/Kconfig: Drop unused DEBUG_ACPI
Change-Id: I135f3e6ec5e75df03331c0c46edb0be243af2adb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36498
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05 14:58:11 +00:00
Patrick Rudolph baa8c7819c mb/supermicro/x11ssh-tf: Disable i8042 support
Even though the vendor firmware enables the i8042 I/O port, it doesn't
feed valid data to those, but instead uses USB HID devices.

Disable the KBC port in SuperI/O and report no KCS port using FADT.

Fixes:
* Fixes error message in Linux that i8042 keyboard couldn't be enabled.

Tested on Supermicro X11SSH-TF:
The virtual remote managment console still works.

Change-Id: I1cdf648aa5bf1d0ec48520fa1e45bdaf043cb45d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-05 14:49:31 +00:00
Kyösti Mälkki 00f0de3e14 drivers/pc80: Remove UDELAY_TIMER2
Change-Id: Ibc0a5f6e7be78be15f56b252be45a288b925183a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36534
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05 14:38:52 +00:00
Kyösti Mälkki 385ea8219d drivers/pc80: Remove UDELAY_IO
Change-Id: I3ab62d9b1caa23305ad3b859e3c1949784ae0464
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-11-05 14:38:35 +00:00
Kyösti Mälkki 092fe558ee intel/i440bx: Switch to UDELAY_TSC and TSC_MONOTONIC_TIMER
Note that due to UNKNOWN_TSC_RATE, each stage will have
a slow run of calibrate_tsc_with_pit(). This is easy enough
to fix with followup implementation of tsc_freq_mhz() for
the cpu.

Change-Id: I0f5e16993e19342dfc4801663e0025bb4cee022a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36525
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05 14:38:17 +00:00
Kyösti Mälkki fe3250dbe6 bootblock: Add TS_START_BOOTBLOCK and TS_END_BOOTBLOCK
Change-Id: I5617e5d9b7238ad7a894934910a3eae742d2d22d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36594
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-11-05 13:42:10 +00:00
Kyösti Mälkki cc5193604f cpu/ti/am335x: Extend monotonic timer to early stages
It is actually all completely broken, dmtimer.c is
not really implemented.

Change-Id: Ifb3f624930c9ef663fae30cd5ddcb1d3d46f06b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-05 13:41:37 +00:00
Arthur Heymans acc88f8e66 drivers/intel/fsp2_0: Hide CONFIG_FSP_CAR
CONFIG_FSP_CAR should not be a user visible option, but depends on the
choice presented in the soc Kconfig.

This also removes the dependencies on ADD_FSP_BINARIES. You need to
included those for other stages too so there is no need to make this
requirement explicit for FSP-T.

Change-Id: Ida32e9c4f5839aef4d4deb7a1c7fabe6335a5d2a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2019-11-05 09:49:08 +00:00
Arthur Heymans 127b820d24 soc/intel/common: Don't link CAR teardown in romstage
This is done in postcar stage. This also assumes CAR tear down will
always be done in postcar stage.

Change-Id: I0ff1624c20b9649ca0a8fa31c342bf99530076d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-11-05 09:40:44 +00:00
Peichao Wang 1e07d40027 mb/google/kahlee/treeya: Update STAPM parameters for Treeya
Tune stapm percentage from 80 to 68 and time from 250 second
to 90 second make them meet Lenovo temperature spec.

BUG=b:143859022
TEST=build firmware and install it to DUT and run fishbowl 1000,
check temperature whether meets spec.

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I254140c9d242ed918b3b689d4fb4a1d0e871cd55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2019-11-05 03:09:19 +00:00
Maxim Polyakov 3a28673293 mb/asrock/h110m/devicetree: fix VR config info
Removes unnecessary information about the Ring Sliced VR configuration
from another board with FSP1.1 (which is no longer supported).

Change-Id: Ia2b90d9ede782852c2127da972333bada378b217
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-04 22:09:46 +00:00
Maxim Polyakov 0dd8fe7ec3 superio/nuvoton/nct5539d: use SuperIO ACPI generator
Adds SuperIO SSDT ACPI generator[1] support.
Not tested on real hardware.

[1] https://review.coreboot.org/c/coreboot/+/33033

Change-Id: If9fd56efd40ee0f860e206882418c8bdc7c16802
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2019-11-04 22:08:13 +00:00