Because the EFS is now fixed at 0xff020000, the ChromeOS RO region needs
to be moved to the bottom of the ROM area to cover that space.
The RO Region 6MiB, but you can't actually set 6MiB as RO - it's either
4 or 8MiB, so that's adjusted. To leave some room for the RW_LEGACY
region, the two RW regions are adjusted to 3MiB each, which should be
plenty.
The GBB region had to be moved from the front of the WP_RO region to the
end to avoid conflicting with the EFS, which needs to be inside the
coreboot cbfs area.
Also get rid of AMD_FWM_POSITION_INDEX. The FWM position is no longer
needed.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I683155ec0f4e6a62d862b9e2fa76af45f4cd5493
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Update the mem_parts_used.txt, generate Makefile.inc and
dram_id.generated.txt for this part.
DRAM Part Name ID to assign
MT62F1G32D2DS-026 WT:B 4 (0100)
K3KL8L80CM-MGCT 4 (0100)
H58G56BK7BX068 4 (0100)
BUG=b:259467147
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I204e871129a1b15d7c373d579e10a7b9ab6deabe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71906
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
To make the code slightly easier to read, add a comment about the scope
to the #endif of the outer #ifdef block.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic2bc83c77750cd8a509f4755fdfa4daaf082d754
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Needs to be selected for ChromeOS mainboards even for non-ChromeOS
builds, else Thunderbolt/USB4 doesn't work under Windows (and likely
Linux as well).
TEST=build/boot Windows on drobit/banshee, verify TB functional
Change-Id: Iee3f99840f0c6cc384d9fdef6dff55bcbfc0380f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72140
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Possible Buffer Overflow - Array Index Out of Bounds. Array
regions size is 256 but 'i' iterates from 0 to 256.
Found-by: Klockwork
BUG=None
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Iee45a5821b9dd3f9e6f9816599beebf34555426d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72049
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the unused fields that were previously used for PCNT and PWRS.
The LIDS field is only used in the ACPI code, but keep if for now, since
it would require a bigger rework to remove it from the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b172214998818f841f5694f47815eddfaf9deaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72139
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the unused fields that were previously used for PCNT and PWRS.
The LIDS field is only used in the ACPI code, but keep if for now, since
it would require a bigger rework to remove it from the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I79509146431e4584e50af4477f3f50dc3cf01bcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72138
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 197d550d06.
Reason for revert: breaks TBT and TypeC display on Brya0
Bug=265375098
Branch=firmware-brya-14505.B
Test=Build and boot Skolas board with Brya0 image. Test TBT
and TypeC display functionality.
Change-Id: Ia0283b023949476e90edff7151d605fa36331bfd
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72081
Reviewed-by: Prashant Malani <pmalani@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This patch adds new macros (i.e. SUS Power Failure and Power Failure)
from the APL EDS vol 1 (doc 569262) to be able to implement common
code API to clear the power failure status bits.
Note: as per the EDS those newly added power management failure bits
are RO and shouldn't change any functionality of the existing APL SoC
code. The reason behind adding those macro definitions is to fix the
compilation issue due to code change targeted for the Intel SKL and
Xeon-SP.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0bbf11ada2b2f8735173be69ad157b8055021126
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72130
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds new macros (i.e. SUS Power Failure and Power Failure)
from the DNV EDS vol (doc 558579) to be able to implement common
code API to clear the power failure status bits.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6ed962eae79154a8faea382dbe8367133cb05eda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Enable early POST code display on this variant using
the common mc_apl1 baseboard functionality.
BUG=none
TEST=Boot on mc_apl6 and observe that POST codes are
displayed before DRAM training.
Change-Id: I2a52c241c383f8ebcf05052e9bc0ba13e63e3728
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Move logic previously used only in the mc_apl2 variant to
the mainboard level so that other variants can also make
use of it without code duplication.
This functionality on the mc_apl6 variant will be enabled
in a follow-up patch.
BUG=none
TEST=Boot on siemens/mc_apl2 and observe that the POST
codes are displayed before DRAM training.
Change-Id: I762e328ad06c047d911ce1fc40f12a66cbd14e11
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Remove AHCI_ROM_FILE since it's not used and there is no ahci.bin file.
Change-Id: I008c6ac78957500d4ce301fe70f5b6d4a549b573
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch fixes the alignment of the PMC macros defined in the
pm.h file.
Change-Id: Ib5ff87e2f6524ca1be69027080149a3fbe2df7d9
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72158
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch fixes the alignment of the PMC macros defined in the
pm.h file.
Change-Id: I9a55e1b099a53180e40eedcc52120d65558e7f8b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72157
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch fixes the alignment of the PMC macros defined in the
pm.h file.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia8d35a5d104658b7900fde7f7b8c6f88530a614e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72129
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update setting for touchpad I2C frequency and hold time to meet touchpad
i2c SPEC.
- Frequency: 380 ~ 400 kHz
- hold time : 0.3 ~ 0.9 us
BUG=b:261159229
TEST=On frostflow, touchpad i2c spec from EE measure
Frequencies: I2C0 (Touchpad): 393.7 kHz
Hold time = 0.604 us
Change-Id: Iecf4960a12aa56ac307fb9022e47c4e94a2551c1
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72114
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Even though the register name begins with ESPI, it resides in the SPI
registers and not in the eSPI registers, so add a comment to point this
out to hopefully avoid some confusion.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9f8d15ceb98f51aad0816021f98ec5c78953e7f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Checked against document #57396 revision 1.52 and removed the
DIS_ESPI_MASCTL_REG_WR define, since that bit is marked as reserved.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e8b1c65118b4e85e7934e822a7a7e329746a88d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Checked against both documents #57019 revision 1.59 and #57396 revision
1.50 that the definitions and the code still apply to Phoenix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id65301ec730793f41044696f2e99356f2e899137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C
and ACPI code, so they can be removed. Also remove the unused fields
that were previously used for PCNT and PWRS. The LIDS field is only used
in the ACPI code, but keep if for now, since it would require a bigger
rework to remove it from the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie1c3c25591deadb27b7bf38a81dcd6fe746de55b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72096
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C
and ACPI code, so they can be removed. Also remove the unused fields
that were previously used for PCNT and PWRS. The LIDS field is only used
in the ACPI code, but keep if for now, since it would require a bigger
rework to remove it from the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5a9b0a24f57a81b98c7553517fe5f25ff63c5316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72095
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C
and ACPI code, so they can be removed. Also remove the unused fields
that were previously used for PCNT and PWRS. The LIDS field is only used
in the ACPI code, but keep if for now, since it would require a bigger
rework to remove it from the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I884d6a7dedb73028f8942fdda86b0c9910fa996a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72094
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
From Cezanne on, the TMPS, TCRT and TPSV fields are unused in both the C
and ACPI code, so they can be removed. Also remove the unused fields
that were previously used for PCNT and PWRS. The LIDS field is only used
in the ACPI code, but keep if for now, since it would require a bigger
rework to remove it from the global NVS.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4034e959d167fb1e08ee5b15e21fb93bc89db8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72093
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All field definitions in the IndexField object match both the info in
the PPR #57243 revision 3.02 and also match the defines in soc/amd/
mendocino/include/soc/amd_pci_int_defs.h. The IndexFieldvonly defines
the subset of the IRQ mapping registers that are used or likely needed
in the future. This is handled in the same way for the other AMD SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b0adfecc99945de69b4853f4423b4c10951d3e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72092
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the addition of the mc_ehl3 board variant, a few
points about commenting the code arose either from the
review or during the implementation itself.
This patch unifies structure of these files, which
have a similar structure across more Siemens boards
utilizing the PTN3460 eDP-to-LVDS bridge.
BUG=none
TEST=Check that images for the affected boards can be
built.
Change-Id: I59820362e1f87e296c5548b9c3cecba4d2710fe7
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72068
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board contains in addition to its base variant, mc_ehl2,
an LCD panel driven through the PTN3460 eDP-to-LVDS bridge.
This patch enables the PTN3460 support by adding the device to
devicetree.cb and board-specific configuration parameters in
lcd_panel.c, based upon a similar implementation in siemens/mc_apl7.
BUG=none
TEST=Boot with the LCD panel attached and observe whether
the picture is stable and free of artifacts coming from wrong
resolution, timing etc.
Change-Id: Ib8a1a6f47053406e42554c2dd33684165d54be08
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The {read,write}{16,32}() functions used in this file come from the
mmio.h header, so include it directly.
BUG=none
TEST=Read out the SD card controller (device 1a.1) PCI registers
in Linux and check whether the values reflect the ones defined
in this file.
Change-Id: Iff7b55ef2bf98371b7d7d9114ccf3ebed64772a2
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72009
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Use acpi_align_current to align the ACPI tables on a 16 byte boundary.
This changes the alignment of the HEST, IVRS, SRAT and SLIT tables from
8 bytes to 16 bytes. The alignment of the ALIB and PSTATE SSDT tables
was already 16 bytes before, so the alignment of those isn't changed.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8933e3731b67012bcae0773db2f7f8de7cd31b56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72055
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to
control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP.
This new option is hooked with `SkipMbpHob` UPD and is always
disabled for ChromeOS platforms.
This made skip_mbp_hob SOC chip config variable redundant
which is also removed as part of this change.
BUG=none
TEST=Build and boot to Google/Rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Iaba1ea29a92a63d2b287e1ccdea1a81ec07b9971
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Currently most of the FSP debug messages (when enabled) are truncated
due to insufficient size of cbmem buffer.
Increase premem cbmem console size to 0x16000 bytes and cbmem buffer
size to 0x100000 bytes so that cbmem buffer can contain most of the
debug logs when FSP debug messages are enabled.
BUG=b:265683565
TEST=Verify output of 'cbmem -c' when FSP debug messages are enabled
but MRC debug message.
Note: Still 350/2200 lines of premem messages are missing.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I120423e1dd2bc468cf9cec6da1246ac3c0a155e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72048
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current size of the cbmem buffer (128KB) is insufficient to contain the
complete debug logs which is more than 166KB hence, cbmem console buffer has wound off to contain the maximum possible debug messages within the allocated buffer as results, we are seeing truncated debug message while looking into the cbmem console.
This patch increases cbmem buffer size to 256KB so that the complete
debug log can be stored in it.
BUG=b:265683565
TEST=Make sure that logs from all the boot stages can be seen using
'cbmem -c'.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ibeabb61d60491b831252b7161c9d3181fbe09e73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72047
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Turn on the dxio_tx_vboost_enable for frostflow in coreboot.
It needs to confirm the PCIe Signal Integrity after enabled.
BUG=b:259007881, b:248221908
BRANCH=none
TEST=emerge-skyrim coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Iaac331737c83ac7a4a1261c32151359e126a009e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Intel Ice Lake is unmaintained and the only user of this platform ever
was the Intel CRB (Customer Reference Board). As it looks like, it was
never ready for production as only engineering sample CPUIDs are
supported.
As announced in the 4.19 release notes, remove support for Intel
Icelake code and move any maintenance on the 4.19 branch.
This affects the following components and their related code:
* Intel Ice Lake SoC
* Intel Ice Lake CRB mainboard
* Documentation
Change-Id: Ia796d4dc217bbcc3bbd9522809ccff5a46938094
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72008
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Turn on the dxio_tx_vboost_enable for markarth in coreboot.
It needs to confirm the PCIe Signal Integrity after enabled.
BUG=b:263534907, b:263216451
BRANCH=none
TEST=emerge-skyrim coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I0798c1d9788e1911c2643bf387722b072aa79045
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Chao Gui <chaogui@google.com>
Martin Roth