As with other macros, convert PAD_CFG0_ROUTE_* to PAD_IRQ_ROUTE() to
make the code in gpio_defs.h cleaner.
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard
does not change.
Change-Id: Iadc9c4b3c96ae04c56d060cb060737a8eba7f165
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41034
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Converts PAD_CFG0_RX_POL_* macros to PAD_RX_POL() to make the code
cleaner and reduce the length of the macro.
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard
does not change.
Change-Id: I09a048fd38ccb994f53c8829c549bc2b368fa546
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41033
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Converts PAD_CFG0_TRIG_ * macros to PAD_TRIG() to make the code cleaner
and reduce the length of the macro, which is often used.
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 & T10-TNI carrierboard
does not change.
Change-Id: I9e1b4118fd6c6f0d58ee38a743aa8c27535f0dd9
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41032
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current the common soc code automatically selects PCIEXP_CLK_PM and
PCIEXP_L1_SUB_STATE which breaks booting Windows with a PCIE NVIDIA
graphics card attached on mainboards that do not have a CLKREQ# signal.
This is commonly used on server and workstations boards where the
additional power savings of L1 substate are not required.
Make the PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE default y but do not
select it anymore by the soc code, thus we can disable it in the
mainboard code.
Tested on CFL with Windows 10.
Change-Id: I025e13d6d8183256647e4c034e31bafa235f7eb7
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41696
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Platform HOBs (in particular IIO_UDS and MemoryMap HOBs) are of HOB type
HOB_TYPE_GUID_EXTENSION, therefore they do not have resource structure.
Remove the erroneous code related to resource structure.
Remove unnecessary function prototypes from header files, and define them
as static in hob_display.c.
Since we have the HOB pointer, there is not need to search HOB by GUID.
Remove unnecessary calling of fsp_find_extension_hob_by_guid().
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: Ib99bce39e6eb2aeb95242dfba36774653bbe91fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43335
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CPX-SP FSP ww28 release adds UPDs to allow enablement of VT-d and VMX.
Also update IIO UDS HOB definition file accordingly.
Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG.
Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel
is that they will converge to use FSPM_CONFIG over time. So both will
co-exist for some time. Today coreboot common code expects FSP_M_CONFIG.
Accomodate this situation in FspmUpd.h.
The CPX-SP soc code is updated accordingly.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: If6d0a041eaad9eb2f811e74d219fff1cc38e95a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
On ChromeOS systems with a serial-enabled BIOS and vboot writing a new
firmware image to the Chrome EC, it was possible for the TCO watchdog
timer to trip 2 times before tco_configure() was called in romstage.
This caused an extra reboot of the system (at a rather inopportune time)
and because the EC didn't perform a full reset, the system boots into
recovery mode.
This patch moves the call to tco_configure() for Tiger Lake from
romstage to bootblock, in order to make sure the TCO watchdog timer is
halted before vboot_sync_ec() runs in romstage. It should be harmless to
configure the TCO device earlier in the boot flow.
BUG=b:160272400
TEST=boot Volteer (to a non-recovery kernel!) with a freshly imaged EC
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iefdc2c861ab8b5fde7f736c04149be7de7b3ae0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43313
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds Type-C Intel Input Output Manager(IOM) device with HID
INTC1072. It provides MMIO range from 0xfbc10000 with size 0x1600.
Intel Input Output Manager(IOM) kernel driver reads relevant
information such as Type-C port status (whether a device is connected
to a Type-C port or not) and the activity type on the Type-C ports
(such as USB, Display Port, Thunderbolt) using this memory resource.
BUG=b:156016218
TEST=Able to detect USB, TBT and USB4 on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ic733e831643bda6e052edf797ba0e6206eb4ddd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41762
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds Type-C IO Manageability engine base address and size.
Tigerlake EDS(#575681) section 3.4.3 describes host bridge
REGBAR(MCHBAR) + 7110h for IOM REGBAR with size 1600h. IOM has a
port ID 0xc1. MCHBAR is programmed with 0xfedc0000. IOM REGBAR is
determined from mmio (MCHBAR + 0x7110), which has value 0xfb000000.
IOM has base address 0xfbc10000 from IOM REGBAR + (0xc1 << 16).
BUG=🅱️156016218
TEST=Built and booted on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41759
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new IGD device ID for new Tigerlake SKU support.
BUG=b:160394260
Branch=None
TEST=build, boot and check IGD device is reported.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I1903d513b61655d0e939f80b0fd0108091fdd7e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Ia314148abc900685d85aede3add480614fa8e99c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner
This reduces the differences between Bay Trail and Braswell.
The resulting binary changes, but it shouldn't matter.
Change-Id: Ic930ab7eee265e86a7cc1095021e3744885f2c25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
This can result in accesses outside array bounds. Copy what Braswell
does, which is slightly safer.
Change-Id: If3d6f4e1f8921f0be7f4e5e438b7e73c46b8ef95
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I3d4c1285bdc4b061383b7bb6262f69671166b9c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This reduces the differences between Bay Trail and Braswell.
Change-Id: I60e4db72eed17cdeebd30b010f351e1ffc4187e3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The PCI COMMAND register is 16 bits wide, so do not use 32-bit ops.
Change-Id: I1baba632bda4a50d5279ca3659047d1dd1e8da34
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Intel Dynamic Tuning Technology is the name of a PCI device on some
Intel SoCs. This minimal PCI driver is only used now for SSDT generation
on TGL devices.
Change-Id: Ib52f35e4e020ca3e6ab8b32cc3bf7df36041926e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41893
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change disables Thunderbolt PCIe root ports bus master before
handing over to payload in order to mitigate the threat from the
unauthorized external DMA. In this state, the PCIe root ports would
be considered as trusted to not forward any DMA transactions to
downstream endpoint devices.
BUG=b:141609884
TEST=Verified PCIe resource has been allocated properly and USB behind
Thunderbolt dock is enumerated successfully.
Change-Id: I9650b9dd4df1f9bee53ae3737b7bf60b2ef8017b
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
For both Tiger Lake and Jasper Lake, add the DEVFN for Image Processing
Unit (IPU) to soc_acpi_name, which is set to return "IPU0".
Change-Id: Ib11be5be7fbaec688d8788945a3bcab3f8d834a1
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42878
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a minimal PCI driver for Intel's IPU, this allows devices to be
added underneath it in the devicetree.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I531b293634a5d40112dc6af7b33fedb5e13f35e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42812
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL:
1. MT53E512M64D4NW-046 WT:E
2. MT53E1G64D8NW-046 WT:E
BUG=b:159195585,b:152936481,b:156435028
TEST=build.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If69087e5e189b3e0f70e5f1afbfe3f884173d3b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The `ENABLE_SMBUS_METHODS` symbol is not defined anywhere, so this code
isn't even being tested. So, throw it into the bitbucket before it rots
any further. If anyone needs that code ever again, it's in git history.
Change-Id: I22e3f1ad54e81f811c9660d54f3765f3c6b83f01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In some cases, the SoC did not even select `REG_SCRIPT` in Kconfig.
Change-Id: I617f332b80c534997e06a91247d1be90a85573be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Since coreboot is initializing uart for debug logs, fsp should not reinitialize it.
Thus we need to set FSP UPD to skip Uart init in FSP and use settings done by coreboot
BUG=None
BRANCH=None
TEST=FSP is able to push debug logs on UART with this setting
Cq-Depend: TBD
Change-Id: I0fda2ace3b1f63159e9809d6a3044a3bad452f07
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Fix a typo to use CONFIG_DISPLAY_HOBS instead of CONFIG_DISPLAY_HOB.
Build hob display into romstage, in addition to ramstage.
Memory map HOB data is a big structure. Update the soc_display_memmap_hob()
to assist trouble shooting of FSP interface.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iece745fe21d11b4a470ba8318201bb6e68c5da26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42841
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These changes are in accordance with the documentation:
[*] page 208-209
Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual,
Volume 4: Model-Specific Registers. May 2019.
Order Number: 335592-070US
Tested on OCP Tioga Pass and Delta Lake.
Change-Id: I8c2eac055a065c06859a3cb7b48ed59f15ae2fc4
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42901
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A UPD HybridStorageMode allows a platform to dynamically configure the
PCIe strap configuration required if an Optane device is connected.
The strap configuration is done by HECI commands between FSP and CSE to
override the default PCIe strap value, and the updated strap value is
stored in SPI RW data to be used on the next boot.
CSE Lite supports the strap override when running on CSE RW partition,
while CSE RO partition does not support it because CSE RO is not allowed
to access SPI RW data. The strap override failure on CSE RO causes FSP
not initializing PCH Clkreq and PCIe port mapping and this results NVMe
and Optane initialization failure.
By disabling HybridStorageMode in case of CSE RO boot, NVMe detection is
done by the default PCIe configuration and Optane is detected as a
single NVMe storage device on CSE RO boot in recovery mode. Both NVMe
and Optane devices detection as well as OS installation to these storage
devices are verified on CSE RO boot in recovery mode.
BUG=b:158643194
TEST=boot and verified with tglrvp and volteer in recovery mode
Cq-Depend: chrome-internal:3100721
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I5397cfc007069debe3701bf1e38e81bd17a29f0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42282
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Time Window Tau bits are only supported by Comet Lake/Cannon Lake
onwards, so skip setting those bits for earlier SoCs.
Change-Id: Iff899ee8280a9b9bbcea57d4e98b92d5410be21d
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This is a W/A to avoid a communication issue with CSE Lite over Heci
interface. This will help to avoid boot failures with CSE Lite until
the permanent fix is available.
BUG=b:159884143
TEST=build and boot volteer with serial and non-serial image
Change-Id: Ib136a2154b36c63c7147bbcfbf1ca7beac3a5685
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42790
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook up the FSP UPD
Change-Id: I6b479bfc83492440eac97cdc8dcc560b6abf4fdf
Signed-off-by: Jonas Loeffelholz <Jonas.Loeffelholz@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42803
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Many previous versions of this function would return early if tcc_offset
is 0. This adds that logic back in.
Change-Id: Ibc529520a4e74608cb5d20e5a6e8fc2c727c903c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Use some defines as well for clarity.
Change-Id: I83204a1a39534066a5f32f6e33a1bed0c827392f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42898
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds Platform-Wide _OSC capabilities for native USB4
support. There is Engineering Change Request (ECR) with _OSC addition
for OSPM USB support. ACPI section 6.2.11.1.13 is modified with bit 18
as native USB4 support. The OS sets this bit to indicate support for
an OSPM-native USB4 Connection Manager which handles USB4 connection
events and link management. The OS use the _OSC mechanism and the bit
defined in this ECR to obtain configuration and connection management
capabilities of USB4 connections. This change also fixs the byte index
for the DWord-addressable field CDW3 from the capabilities buffer.
BUG=b:140645231
TEST=Check Type C device all ports connection/enumeration with SW CM.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I1b561ea5a0a6b440cca3152cc150f31abf7766ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Align support for enable wake-on-usb attach/detach as was
introduced in Skylake in
`commit 3bfe3404df32ca226c624be0435c640bf1ebeae7`.
This adds the USB Wake Enable Setup (UWES) ASL blocks
required to inform the OS about plug wake events bits
being set in the PORTSCN register configured by devicetree.
BUG=b:159187889
BRANCH=none
TEST=none
Change-Id: I6c63d226e5acadff04486c8a6764fb715a0ac051
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This enables Thermal Control Circuit (TCC) activation feature to set
tcc_offset value to new value in devicetree.
BUG=None
BRANCH=None
TEST=Built for dedede platform and verified the MSR value
Change-Id: I58e4fa362f20efeef84e06e64d70ee7c4f9554d6
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
