Commit Graph

33035 Commits

Author SHA1 Message Date
Angel Pons 4684dc0c63 util/inteltool: Add missing entry for WPT-LP Premium
Tested on a laptop with an i7-5500U processor, the device is now found.

Change-Id: I49ddec862520d0d5492d78fec89efd841c141790
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-24 12:48:09 +00:00
Joel Kitching a6531a335c vboot: remove rogue vboot_struct.h include
As part of vboot1 deprecation, remove an unused vboot_struct.h
include.  coreboot is now free of vboot1 data structure use.
One vboot_api.h include remains as part of security/vboot/ec_sync.c.

BUG=b:124141368
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I042d692aa252f8f859d4005455eb6a2eabc24a87
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-24 12:47:55 +00:00
Dtrain Hsu 0d4dd167f5 mb/google/sarien: Remove MAC address pass through
Remove MAC address pass through because when MAC address pass through setting
change to "Use dock built-in MAC address", the MAC address always keeps the VPD
value.

BUG=b:149813043
TEST=tested on sarien and the result as below.
  (Option)                          (Result)
- Use pre-assigned MAC address    : Pass
- Use Chromebook built-in address : Pass
- Use dock built-in MAC address   : Pass

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ia85ef6ed0c4db82301375edd0968cf7dd2f62dc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-02-24 12:47:31 +00:00
Evgeny Zinoviev 8c4c370030 util/ifdtool: Mention MeDisable in help text
The -M option of ifdtool sets not only AltMeDisable bit, but also
MeDisable bit in ICH0 and MCH0 straps. Make it obvious and mention
in the help message.

Change-Id: I9dba2fa6509a9c833f72414367944bc606671e7b
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-24 12:47:09 +00:00
Eric Lai 94022a0abf mb/google/drallion: Set GPP_G4 and GPP_G6 to NC pin
Follow latest HW schematics to set GPP_G4 and GPP_G6 to NC pin.
This can save 1mW power comsumption.

BUG=b:149289256
TEST=NA

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib3bf8b8f922a350d2b73ef5c9e9cf1b6e2c0f657
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-24 12:46:50 +00:00
Matt DeVillier 0868f96439 mb/google/{auron,slippy}/ec: clear pending events on S3 wakeup
Commit 6ae8b50 [chromeec: Depend on events_copy_b to identify wake source]
partially broke resume from suspend on Auron and Slippy variants when
multiple events exist in the EC event queue. In the case of the device
suspending manually and then subsequently having the lid closed, the device
will be stuck in a resume/suspend/resume loop until the device is forcibly
powered down.

Mitigate this by clearing any pending EC events on S3 wakeup.

Test: build/boot several Auron/Slippy variants, test suspend/resume functional
with both single and multiple events in EC event queue.

Change-Id: I7ec9ec575d41c5b7522c4e13fc32b0b7c77d20d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-02-24 12:45:48 +00:00
Karthikeyan Ramasubramanian 96eceba314 mb/google/dedede: Add waddledoo variant
Add initial support for waddledoo board.

BUG=None
TEST=Build the mainboard and variant board.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8ab4d52c97b1cfb5549d2fce4b931748a1b1ff1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-24 12:31:23 +00:00
Karthikeyan Ramasubramanian be6583ae5c mb/google/dedede: Add EMMC configuration
Turn on EMMC device and enable the HS400 mode. Configure the GPIOs
associated with EMMC.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic27c68f4622eec5b2930dc38186b82d895d3f67c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-02-24 12:31:12 +00:00
Karthikeyan Ramasubramanian 7225ed6035 mb/google/dedede: Add USB configuration
Add USB port configuration in devicetree. Configure USB Over-Current (OC)
GPIOs.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I19f7563013c7d702d52b7f34a207a34abe308621
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-02-24 12:30:57 +00:00
Dtrain Hsu 5cfe449814 mb/google/drallion: Remove MAC address pass through
Remove MAC address pass through because when MAC address pass through setting
change to "Use dock built-in MAC address", the MAC address always keeps the VPD
value.

BUG=b:147994020
TEST=tested on drallion and the result as below.
   (Option)                          (Result)
 - Use pre-assigned MAC address    : Pass
 - Use Chromebook built-in address : Pass
 - Use dock built-in MAC address   : Pass

Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I1f58e98187feb4e428ca75f7e82c464567528526
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
2020-02-24 12:30:41 +00:00
Sridhar Siricilla 182a0aee3d soc/intel/cnl: Rename hfsts into me_hfsts
Remove me_hfs3 union from cnl/me.c since it's already defined in soc/me.h.
Rename below union tags for consistency:
	hfsts2 -> me_hfsts2
	hfsts3 -> me_hfsts3
	hfsts4 -> me_hfsts4
	hfsts5 -> me_hfsts5
	hfsts6 -> me_hfsts6

TEST=Verified on hatch

Change-Id: If81edbad0322425ee3e96c55a9c84a5087604308
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-24 10:32:41 +00:00
Subrata Banik 4ab7ef93ee soc/intel/apollolake: Make SMI_STS offset macro definition consistent
This patch makes all bit field macro definition for SMI_STS register
(offset 0x44) be consistent i.e. ending with "_STS_BIT".

Also modified relevant files where those macros are getting used.

Change-Id: Ibe3fbb459c106a3a58cd9a8b6eb3d7ee92e6ed82
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-23 13:41:36 +00:00
Ronald G. Minnich f5529d9edc cbfs: allow uncompressed payloads
Change-Id: I8261bc28e5bc9aa32db1dccef7035486995c9873
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39051
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-22 22:38:27 +00:00
Paul Fagerburg 291a014e15 util/mainboard/google: deduplicate create_coreboot_variant.sh
create_coreboot_variant.sh and kconfig.py have moved to the chromium
repo, in src/platform/dev/contrib/variant (see crrev.com/c/2052338),
so remove them from the coreboot repo.

BUG=b:149410618
BRANCH=None
TEST=N/A

Cq-Depend: chromium:2052338
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: Ie27f68bfd978be5e2b1a2f0789d574749825f6fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-02-21 16:55:58 +00:00
Eugene Myers 17f0f01188 cpu/x86/smm: Convert C++ style comment
Originally, this patch made 'BIOS' uppercase in the referenced comment
and converted the C++ style to be consistent with the remainder of
the function.  Somewhere, the 'BIOS' became uppercase creating a merge
conflict.

Now this CL converts the C++ style to be consistent with the remainder
of the comments.

Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Change-Id: I85d78b5e08a7643c3d87e3daf353d6b3ba8d306b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38854
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-21 09:02:57 +00:00
Eugene Myers 9d4f94af24 security/intel/stm: Use depends on ENABLE_VMX
The STM is a part of the core VTx and using ENABLE_VMX will make the
STM option available for any configuration that has an Intel
processor that supports VTx.

Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Change-Id: I57ff82754e6c692c8722d41f812e35940346888a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38852
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-21 09:02:06 +00:00
Eugene Myers 5544f62746 security/intel/stm: Check for processor STM support
Check to ensure that dual monitor mode is supported on the
current processor. Dual monitor mode is normally supported on
any Intel x86 processor that has VTx support.  The STM is
a hypervisor that executes in SMM dual monitor mode.  This
check should fail only in the rare case were dual monitor mode
is disabled.  If the check fails, then the STM will not
be initialized by coreboot.

Signed-off-by: Eugene D. Myers <edmyers@tycho.nsa.gov>
Change-Id: I518bb2aa1bdec94b5b6d5e991d7575257f3dc6e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-21 09:01:57 +00:00
James Ye 2b6d249632 nb/intel/snb: Add PCI routing table for PEG root ports
Previously the PRTs were defined in southbridge code (8014714
southbridge/intel/bd82x6x/acpi: Fix IRQ warnings), but this was lost
when southbridge PRTs became autogenerated. Add the proper PRTs for the
PCI express for graphics root ports.

This (again) fixes warnings issued by Linux for interrupts on secondary
functions of devices on the PEG ports, such as the HDMI audio controller
on graphics cards.

    pcieport 0000:00:01.0: can't derive routing for PCI INT B
    snd_hda_intel 0000:01:00.1: PCI INT B: no GSI

Tested with GIGABYTE P67A-UD3R (CB:31363) with Radeon HD 5670.

Change-Id: Ic429ec2fdeadb9dab1c03916974e173004d6cd16
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-02-21 08:54:42 +00:00
Marshall Dawson dc83cd2ac1 soc/amd/stoneyridge: Remove TODO for file extensions
The comment is no longer relevant.  Perhaps the intention had been
to modify the names of the files delivered from AMD in order to
simplify Makefile.inc.

AMD firmware is distributed via the new amd_blobs repo and the
filenames match the blobs as they are released.  Multiple Family 15h
devices are supported by this directory and their SMU Firmwares do
not all follow identical naming convention.

Keep the existing functionality and reword the comment.

BUG=b:120118850

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ifbf8e2286f34bc37a6178c37f8c412ec51ee02c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-20 15:22:01 +00:00
Patrick Georgi cbc5b99ac9 util/lint: Allow non-option carrying named choices
named choices can be overridden with a default later-on:

choice FOO
  config A
  config B
  config C
endchoice

...

if BOARD_FOO
choice FOO
  default A
endchoice
endif

Reflect that.

Change-Id: I6662e19685f6ab0b84c78b30aedc266c0e176039
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29813
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-19 15:13:37 +00:00
Subrata Banik 0d866f8cd8 soc/intel/common/block/lpc: Drop unnecessary helper function
This patch removes unnecessary helper function pch_lpc_interrupt_init()
and directly uses soc_pch_pirq_init() function to avoid redundant
device NULL check.

TEST=Able to build and boot CML platform.

Change-Id: I3d11afb7e98f9b7f84beb2fdf308bbffeb3bbff7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38952
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-19 12:11:40 +00:00
Meera Ravindranath f71c6ae216 soc/tigerlake: Add IRQ header and ACPI support for JSP
Tigerlake irq.h and pci_irqs.asl have differences compared to
Jasperlake. Hence renaming irq.h as irq_tgl.h and pci_irqs.asl as
pci_irqs_tgl.asl

Also adding a new file irq_jsl.h and pci_irqs_jsl.asl for Jasperlake
SoC and allowing irq.h and pci_irqs.asl to choose the correct file based
on SoC selected.

BUG=None
BRANCH=None
TEST=Compilation for Jasperlake board is working

Change-Id: Ia8e88f92929fe40d7be1c28947e005cb0d862fcb
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2020-02-19 12:11:26 +00:00
Evgeny Zinoviev 5efe122b27 Documentation: soc/amd/psp: Use real table markup
Currently, tables on this page are formatted as code blocks with
ASCII tables. Make it real beautiful tables.

Change-Id: I3c46477352b8151f3b0fb0616f909531a0a15c34
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-19 12:10:22 +00:00
Evgeny Zinoviev abe9673774 Documentation: Use inline code block for kernel parameter
Change-Id: I41649d4d0ee0abf9335f6cb3d7b19888c0c62382
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
2020-02-19 12:09:53 +00:00
Nico Huber e549503967 soc/intel/p2sb: Drop unnecessary P2SB_GET_DEV
PCH_DEV_P2SB already covers both __SIMPLE_DEVICE__ cases. The values are
only used for PCI-config access functions, which also check for NULL
when necessary.

The PCI_DEV_INVALID case can't occur by definition, and if we wanted to
check, we could do so at compile time using _Static_assert().

Change-Id: I400fc20133809aaa0fd0519531a62ec9b8812ef1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-19 12:08:53 +00:00
Joel Kitching 172ef5fe61 vboot: remove use of NEED_VB20_INTERNALS switch
The NEED_VB20_INTERNALS switch is being deprecated.
Use the header file vb2_internals_please_do_not_use.h instead.

BUG=b:124141368, chromium:957880
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: Ie35644876178b806fab4f0ce8089a556227312db
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:2055600
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-19 12:08:12 +00:00
Joel Kitching 338e9dcd6b vboot: use vb2api_get_recovery_reason function
Use vb2api_get_recovery_reason() API function rather
than accessing vb2_shared_data internals.

Of all the vanilla verified boot code in coreboot,
this is the last remaining use of vboot's internal
data structures in coreboot.  There remains only one
sole instance in Eltan's code.

BUG=b:124141368, chromium:957880
TEST=make clean && make test-abuild
BRANCH=none

Change-Id: I845c9b14ffa830bc7de28e9a38188f7066871803
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:2055662
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-02-19 12:08:03 +00:00
Joel Kitching 24d994afd2 Update vboot submodule to upstream master
Updating from commit id 0e97e25e:
2020-01-28 02:32:08 +0000 - (2lib: Fix struct vb2_hash the way it was meant to be)

to commit id 8b9732f5:
2020-02-18 05:55:01 +0000 - (vboot: do not call vb2_commit_data at end of VBSLK)

This brings in 36 new commits.

Change-Id: Icb0ab2c82c3264185171a32357944949afd2edce
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-19 12:07:57 +00:00
Angel Pons 52c89d302b mb/intel/glkrvp/chromeos.fmd: Correct indentation
Tested with BUILD_TIMELESS, no changes.

Change-Id: Iaf615e95a30e9c02ad49351a3c0db253ad713ad4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-18 21:31:17 +00:00
Andrey Petrov d1f7c6f286 cpu: Allow to configure microcode at pre-defined address
FSP-T takes microcode pointer and location parameters, and FSP-T is
invoked before CAR is set-up and before memory is trained. So it is not
possible to modify supplied microcode pointer in runtime. Because of
that we have to hardcode the pointer in bootblock.

Also, current FSP-T on Xeons require microcode (it is not optional).
Reasons for that are currently unclear and are being investigated.

However for the present time we need to be able to add microcode at a
certain offset so FSP-T can be used.

TEST=test on OCP TiogaPass board, as well as out-of-tree CPU/board

Change-Id: I6c02601a7ac64078e556e2032baeccaf27f77da2
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-02-18 20:12:14 +00:00
Evgeny Zinoviev 286b07ca33 Documentation: Fix style issues on Lenovo X301 page
- Fix lists markup
- Some minor fixes in the text (e.g. lowercases)

Change-Id: I812bdbeed6609c31f3428a3020fa4b32ebbb3445
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38948
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-18 19:48:33 +00:00
Patrick Georgi 900a254475 util/amdfwtool: Improve comment's grammar
Change-Id: I2daa57c1982346e48dbd91a94864baf2f11c2129
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reported-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-18 15:33:43 +00:00
Wim Vervoorn 5bf7b1ac69 mb/facebook/monolith: Use serial number and UUID from VPD
The serial number and UUID returned by DMI are retrieved from VPD.

The solution supports a 16 character "serial_number" and a 36 character
"UUID" string.

BUG=N/A
TEST=tested on monolith

Change-Id: I0b6ce769cfa81a1e248a35f6149b7d1bbcf1f836
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-18 15:31:26 +00:00
Wim Vervoorn 2e7c2cef15 mb/facebook/monolith: Enable use of VPD
Enable use of VPD for monolith. This will be used to store the UUID and
Serial number.

BUG=N/A
TEST=build

Change-Id: I32b60fef44929c51427a124cbb81e5246db2546c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-02-18 15:30:53 +00:00
Sridhar Siricilla 09ea37172e soc/intel/common: Add function to wait for CSE to enter Soft Temp Disable mode
Below helper function is added:
  cse_wait_com_soft_temp_disable() - It polls for CSE's operation mode
 'Soft Temporary Disable'. CSE enters this mode when it boots from
  RO(BP1) partition. The function must be called after resetting CSE to
  wait for CSE to enter 'Soft Temporary Disable' Mode.

BUG=b:145809764

Change-Id: Ibdcf01f31b0310932b8e834ae83144f8a67f1fef
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-02-18 15:01:09 +00:00
Sridhar Siricilla 206905c309 soc/intel/common: Check prerequisites for HMRFPO_GET_STATUS command
Send HMRFPO_GET_STATUS command when CSE's current working state is Normal.

TEST=Verified on hatch.

Change-Id: I4380e5096c6346d88aae6826d19a2f4ed1e97036
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2020-02-18 15:00:39 +00:00
Usha P 5bf7ffbe08 cpu/x86/name: Make name.c file available in romstage
In this patch, name.c file that includes the function definition for
fill_processor_name which is used by the report_cpu_info function is been
made available in romstage.

This is done to facilitate the report_platform_info to be called from
romstage, as the intention is to move the report_platform_info to romstage
for all SOC's due to the bootblock size constraint.

BUG=None
TEST=Build and boot APL, GLK and CNL platforms.

Change-Id: Ifd6d4b80c2e07d02adaed676a56efeb6fb704552
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-02-18 14:59:48 +00:00
Tim Wawrzynczak eb3cd85610 ec/google/chromeec: Add SSDT generator for ChromeOS EC
Upcoming patches for the Linux kernel (5.6 ?) would like to consume
information about the USB PD ports that are attached to the device. This
information is obtained from the CrOS EC and exposed in the SSDT ACPI
table.

Also, the device enable for this PCI device is moved from ec_lpc.c to
a new file, ec_chip.c, where EC-related ACPI methods can live.  It
still allows other code to call functions on device enable (so that
PnP enable for the LPC device still gets called).

BUG=b:146506369
BRANCH=none
TEST=Verify the SSDT contains the expected information

Change-Id: I729caecd64d9320fb02c0404c8315122f010970b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-18 14:59:17 +00:00
Yu-Ping Wu 214fb9b511 security/vboot: Correct help text of VBOOT_STARTS_IN_ROMSTAGE
Since CB:37231 [1], the vboot working data has been replaced with vboot work
buffer, so corrrect the help text of option VBOOT_STARTS_IN_ROMSTAGE
accordingly.

[1] security/vboot: Remove struct vboot_working_data

BRANCH=none
BUG=chromium:1021452
TEST=none

Change-Id: I80783274179ae7582bbb4c8f9d392895623badce
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
2020-02-18 14:58:52 +00:00
Jonathan A. Kollasch d346a19ded nb/intel/sandybridge: Add Xeon E3-1200 (v1) hostbridge PCI ID
Change-Id: I70187d09ecdaa8149299cdd8f6f8fc9517b05e15
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-18 14:56:26 +00:00
Jonathan A. Kollasch bda161b4b5 nb/intel/sandybridge: use list of northbridge device IDs
Change-Id: Ida311a7b0c1f33b1724a07c7cd64ea9834cfc179
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-18 14:55:15 +00:00
Paul Fagerburg 1e7da75b77 volteer: allow empty SPD_SOURCES
Some Volteer variants might not use SPD files. Allow SPD_SOURCES in
spd/Makefile.inc to be empty.

BUG=None
BRANCH=None
TEST=Build coreboot and see that it builds without error

Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: I5a8231b999e16503867d3c8df571b11fa0c1f6a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-02-18 14:53:47 +00:00
Evgeny Zinoviev b3a247ccca Documentation: mb/lenovo: Make X1 uppercase
x1 -> X1.

Change-Id: Iab28e979102a6f98c41706ac0f483770466385dc
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17 20:22:54 +00:00
Patrick Rudolph f6be41a988 Documentation/lenovo: Replace RST code with markdown
Latest Sphinx supports up path traversal in markdown. Replace old
RST code that's no longer needed to prevent it being copy and pasted.

Change-Id: Ieec5cc1f8d91a7fbc003efae465f61e6b72b39dc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17 20:13:47 +00:00
Patrick Rudolph f9e10f26ba Documentation: Remove confusing xyz0 naming convention for Lenovo devices
Replace xx30 with Ivy_Bridge and xx20 with Sandy_Bridge.
Also add a note that the Ivy_Bridge tutorial doesn't covert T430s and T431s.

Change-Id: I0b65bca83195ec22cc139130e7cb6183c0972484
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38929
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17 20:12:22 +00:00
Elyes HAOUAS 6dc9d0352e treewide: capitalize 'BIOS'
Also replace 'BIOS' by coreboot when the image is 'coreboot.rom'.

Change-Id: I8303b7baa9671f19a036a59775026ffd63c85273
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-02-17 20:11:24 +00:00
Evgeny Zinoviev c7a3152273 Documentation: ifdtool/layout: use real table for FD regions
Current doc transpiles to something completely unreadable.

Change-Id: I197deb52974c88e067bc1615986a42c889214888
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-02-17 20:08:41 +00:00
Felix Held b39bc2510e Documentation/superio: add formatting to generic PNP documentation
Change-Id: Id12ec4d5f11f4285a1379cf32a5d0f6cd2ce9e70
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38519
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-02-17 16:27:24 +00:00
Nicola Corna fab9ae8167 ec/lenovo/h8/acpi: Add alternative Fn-F2 and Fn-F3 layout
thinkpad_acpi maps the battery hotkey (KEY_BATTERY) on scancode 0x01 and
the lock hotkey (KEY_COFFEE) on scancode 0x02.

On the Thinkpad X1 Carbon (and possibly others), the hotkeys for Fn-F2
and Fn-F3 are different from the default one so a new layout has to be
defined.

Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-02-17 16:06:53 +00:00
Nicolò Veronese 8407d4f12e mb/google/slippy: Fix IRQ of the ambient light sensor
Change based on google/auron that is similar to peppy.

This will be helpful for the next follow-up commit that will
add ACPI for the ambient light sensor.

Change-Id: Ib2a8356d261d211d5ed5c0b035c94ec56b9c25b3
Signed-off-by: Nicolò Veronese <nicveronese@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-02-17 16:04:54 +00:00