Commit Graph

55007 Commits

Author SHA1 Message Date
Nick Vaccaro 0863f7cdb2 mb/goog/brya/var/brya0/skolas: Disable HPS GPIOs if HPS_ABSENT
Check FW_CONFIG and disable gpios for HPS if HPS_ABSENT for skolas
and brya0 variants.

BUG=b:311740746
BRANCH=firmware-brya-14505.B
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas
to kernel and verify via "cbmem -c | grep HPS".

Change-Id: I8cbe4f40c41f1d06e8f511c3e88c05984566d441
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-20 14:34:33 +00:00
Nick Vaccaro 6615c60fd5 mb/goog/brya/var/brya0/skolas: Disable LTE GPIOs if LTE_ABSENT
Check FW_CONFIG and disable gpios for LTE if LTE_ABSENT for skolas
and brya0 variants.

BUG=b:311459627
BRANCH=firmware-brya-14505.B
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas
to kernel and verify LTE gpios are disabled via "cbmem -c | grep LTE".

Change-Id: I3f3bc2b536babf71cc484cce02f96f47707f729c
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79122
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-20 14:34:15 +00:00
Nick Vaccaro f6113ececc mb/goog/brya/var/skolas: sync slolas overridetree with brya0
Skolas uses brya0 schematic, so override tree should be almost the same
for brya0 and skolas.  This change sync's the skolas overridetree.cb
with brya0's overridetree.cb.

BUG=b:311722825
BRANCH=firmware-brya-14505.B
TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to
kernel.

Change-Id: I14a2ed803a8ffb8614018af587c66034fb724b38
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-20 14:33:39 +00:00
Maximilian Brune b57f87fb9a sbom/Makefile.inc: Change GOPATH
This changes the path where go installs its packages.
Now the packages are not installed in the users home directory anymore.
This solution is not perfect though, since offline build are still not
possible, because go will fetch the packages at build time.

-modcacherw will create the go files with rw permissions, otherwise
coreboot is not able to delete the files afterwards (make distclean).

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I2a35369628454057ea4758cd1225e57f07cb71c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-20 14:32:54 +00:00
Yidi Lin ec1a880c51 mb/google/geralt: Remove unnecessary delay for MIPI panel
According to eDP panel datasheet[1], the eDP panel needs 0 <= x <=200ms
delay after VDD powering on. The MIPI panel[2] does not need this delay.
Move this delay to eDP path.

[1] NE135FBM-N41 V8.0 Product Spec_P2 20191025.pdf
[2] B5 TV110C9M-LL0 Product Specification Rev.P0

BRANCH=none
BUG=none
TEST=check FW screen
TEST=check timestamp
Before:
  60:device initialization                             696,422 (1)
  15:starting LZMA decompress (ignore for x86)         696,587 (165)
  16:finished LZMA decompress (ignore for x86)         696,675 (88)
  17:starting LZ4 decompress (ignore for x86)          1,340,226 (643,551)

After:
  60:device initialization                             724,259 (1)
  15:starting LZMA decompress (ignore for x86)         724,425 (166)
  16:finished LZMA decompress (ignore for x86)         724,512 (87)
  17:starting LZ4 decompress (ignore for x86)          1,168,176 (443,664)

Change-Id: I92bca5ec8269f4bad4dfab4ee193cdb5665de233
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79109
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-20 09:22:04 +00:00
Jon Murphy 193e9e8529 cross-repo-cherrypick: Update downstream branch
ChromeOS has switched to using the main branch, update accordingly.

BUG=b:294218930
TEST=None

Change-Id: I31f67ef4fb175a4e4896b5bed81d5ae1cdddb827
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79143
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-20 07:40:11 +00:00
Martin Roth b558758554 Documentation/releases: Add 24.02 release notes template
In preparation for the upcoming release, add the template for the
24.02 release and update index.md.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I694142c31ba684e7b94640d55302b2440e25619a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79073
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-19 17:39:12 +00:00
Felix Held a56ff9087b sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetree
Since the HD audio controller in the PCH are always on the same device
functions, the device operations can be statically assigned in the
devicetree and there's no need to bind the host bridge device operations
to the PCI device during runtime via a list of PCI IDs.

TEST=Lenovo X220 still boots to Linux and audio still works

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I9bbbe9f4490dc6fb21174d63d1c8906d69ea3ee0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79118
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-18 16:36:46 +00:00
Felix Held 58a5374d5f sb/intel/bd82x6x: assign PCIe root port ops in chipset devicetree
Since the PCIe root ports in the PCH are always on the same device
functions, the device operations can be statically assigned in the
devicetree and there's no need to bind the host bridge device operations
to the PCI device during runtime via a list of PCI IDs.

TEST=Lenovo X220 still boots to Linux and all PCIe devices on PCH are
visible and working.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I05bfe8db88fd54415f320f32ea147636ca4e0df8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-11-18 16:36:33 +00:00
Felix Held 61f22cff59 nb/intel/sandybridge: assign gma ops in chipset devicetree
Since the integrated GPU is always function 0 of device 2 on bus 0, the
device operations can be statically assigned in the devicetree and
there's no need to bind the host bridge device operations to the PCI
device during runtime via a list of PCI IDs.

TEST=Lenovo X220 still boots to Linux and graphics works in UEFI

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: I20e387e626e19dc441aceda18451186d1e86cd5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79114
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-18 15:38:03 +00:00
Felix Held 4c4d1948ef nb/intel/sandybridge: assign host bridge ops in chipset devicetree
Since the host bridge is always function 0 of device 0 on bus 0, the
device operations can be statically assigned in the devicetree and
there's no need to bind the host bridge device operations to the PCI
device during runtime via a list of PCI IDs.

TEST=Lenovo X220 still boots to Linux

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Icf3d9f8cd2be2f8ef71fd9fdb5f005f3b683332e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79113
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2023-11-18 15:37:50 +00:00
Martin Roth c8dc4a3bd1 util/lint: Add linter to keep selects out of Kconfig.name
While having select statements in Kconfig.name files is valid in the
syntax of the Kconfig language, having the selections split between the
normal Kconfig file and Kconfig.name files makes it harder to see what's
going on.

Kconfig.name files will now be limited to their original purpose of
selecting a particular board or board variant, not actually configuring
that board.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I2aab78e296f2958e77a938b1afa40a25a6aa82b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-18 01:58:24 +00:00
Shelley Chen 7e775cf893 mb/google/brox: Use Ti50 config
Brox is using Ti50, so make sure that we set the right config for that.

BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: If4a16448eebc028b2989c1de150b9e0f9067ee92
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-18 01:54:18 +00:00
Shelley Chen 513d54708d mb/google/brox: Fix GPIO assignments in gpio.h
Assigning the macros in gpio.h to the correct GPIOs.  Also, fixing GPE
configurations so that they are mapped to the proper wake sources
(GPP_B, D, E groups).

BUG=b:300690448
BRANCH=None
TEST=emerge-brox coreboot

Change-Id: I6320cd98e560e514e63c52e173cb7923cfd1cdee
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-18 01:54:03 +00:00
Julius Werner 653f349f2f qualcomm/sc7180: Move QCSDI and increase romstage size by 4KB
We need to increase romstage size a little to make a compiler upgrade
fit (CB:70771). Unfortunately the end of the romstage directly touches
the QCSDI region in the current memlayout, and there is no other way
to reshuffle things to make more space... so we need to move QCSDI out
of the way. This means that anyone who is actually building this
platform with CONFIG_QC_SDI_ENABLE (which requires a proprietary blob
that's not publicly available) will need to recompile their QCSDI binary
to match the new start address.

Change-Id: Iaf13e4001b3c763e3ec59009779931ec75603d5d
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79074
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-18 00:41:53 +00:00
Martin Roth 947eebedcb Docs/releases: Update 4.22 release notes
These should be the final release notes prior to tagging coreboot

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id723f8e1fc92ef1a36e877f48e594eef59b0ba8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79077
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-18 00:26:16 +00:00
Martin Roth 6843755c26 docker/coreboot-sdk: Add perl modules for gcov
These perl modules are needed to run the coverage-report target for
gcov.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If32a42ce17edcbae94394f770c26d3300abebcbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79072
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17 23:46:56 +00:00
Martin Roth 64b340065f Docs/security/vboot: Update list of boards with vboot
Update the vboot board list for the 4.22 release.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I77c5ca2c2c36d8b1ddadad4f15d2d4148ff0b325
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2023-11-17 22:19:04 +00:00
Felix Singer a2dffba45f mb/google/herobrine: Move selects from Kconfig.name to Kconfig
Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.

Change-Id: I25b7adccf60abe515d129f8d00383165eccf6431
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79028
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17 22:18:21 +00:00
Felix Singer e0a1ca5ac9 mb/google/trogdor: Move selects from Kconfig.name to Kconfig
Selects should be done in the Kconfig file instead of Kconfig.name and
not mixed over both files.

Change-Id: I30a15277527a1e423691ff55ff11cc2136cefc90
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-17 22:18:01 +00:00
Felix Singer c541567834 soc/qualcomm/{sc7180,sc7280}: Allow building without QC blobs repo
Building coreboot for the Qualcomm SoCs SC7180 and SC7280 requires to
include the Qualcomm blobs, which requires to accept their license.
However, for various reasons it makes sense to build without blobs, e.g.
static analysis or just build-testing.

So in order to do that, run the steps integrating the Qualcomm blobs
into the coreboot binary only if USE_QC_BLOBS is enabled and also remove
guards which prevent building related mainboards when USE_QC_BLOBS is
not enabled.

Change-Id: I249ac477b8f10e7fa0848e967c23a3b3b9bbd27d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79026
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17 22:17:31 +00:00
Felix Held 8ccd314ce6 nb/amd/pi/00730F01: add CPU and domain ops in devicetree
Add the CPU and PCI domain operation bindings statically in the chipset
devicetree instead of adding them during runtime.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44fa57458c408e74a6341643620c5e9ac1817557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-17 16:28:10 +00:00
Felix Held 1952d13a41 nb/amd/pi/00730F01: restructure chip ops
Since this chip is a SoC and also to bring the chipset devicetree more
in line with the chipset devicetree of Sandy Bridge, merge the chip
operations of the northbridge's root complex and the northbridge itself
into one chip operations structure and use it at the top level of the
devicetree.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-17 16:27:52 +00:00
Felix Held 0010b89c67 nb/amd/pi/00730F01: introduce and use chipset devicetree
BKDG #52740 Rev 3.05 was used as a reference for the SoC's various PCI
devices. The HDA controller in the FCH at function 2 of device 0x14 on
bus 0 was missing in the mainboard's devicetrees.

TEST=PC Engines APU2 still boots and doesn't show any new problems

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79083
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-17 16:27:43 +00:00
Felix Held 10e478c4cf include/device/device: drop HAVE_ACPI_TABLES guards
There's no need to remove the corresponding fields from the
device_operations struct when HAVE_ACPI_TABLES isn't selected.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iac20b6cdc44a5280566ee7003a5ef6fbe913b099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78990
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17 15:13:15 +00:00
Felix Held ab8a094cf0 include/device/device: drop GENERATE_SMBIOS_TABLES guards
There's no need to remove the corresponding fields from the
device_operations struct when GENERATE_SMBIOS_TABLES isn't selected.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifa24d1fd211c263b788046e63de3dd5c54cba801
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-17 15:12:59 +00:00
wuyang5 823f95e8a3 mb/google/corsola: Configure I2C and I2S interface for ALC5650
Configure I2S1 and I2C5 for ALC5650 to support beep sound in
depthcharge.

BRANCH=corsola
BUG=b:305828247
TEST=Verify devbeep in depthcharge console

Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79064
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-11-17 15:03:01 +00:00
Dinesh Gehlot 9664463c71 MAINTAINERS: Add Dinesh Gehlot as MTL SOC and GOOGLE REX MB maintainer
Change-Id: I92d5497644338927b81fbabea2bce45f1e59f0b4
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-17 15:02:35 +00:00
Matt DeVillier a13959e3f7 mb/google/zork/morphius: Drop touchscreen detection
Morphius boards using pre-v3.6 schematics don't have a dedicated GPIO
for touchscreen power/enable, and so fail with runtime detection
enabled. Since it only has one touchscreen option, and no SKUs lack a
touchscreen, we can safely assume it is present in all cases.

TEST=build/boot morphius w/4k screen, verify touchscreen enabled in
cbmem and functional in Linux and Windows.

Change-Id: I13e07e14b5a18fa1dd3b18950cf46e9d7821eedc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-17 12:43:19 +00:00
Martin Roth 0bb9dcce19 util/docker: Switch back to root user in jenkins-node
Leaving the user as coreboot caused the entrypoint to run as coreboot,
which means we couldn't mount directories or run sshd correctly.

Switching to root at the end of the file fixes this.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie10e1d7ad4def0faafe3bcd580a77e23c3bfe948
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79067
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16 23:18:47 +00:00
Maximilian Brune 794d1d7f6c util/ifdtool/ifdtool.c: Add NULL check for fmapname
Some boards (e.g. prodrive/hermes) that do not provide their own FMAP
and therefore have been generated by the build system (+ ifdtool)
experience a failure when trying to build with an IFD that contains
regions which do not have equivalent fmap names (set to NULL).

Therefore add a NULL check for the fmapname and ignore the region if we
do not have an fmapname.

Test: compile prodrive/hermes

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Ib4589b7fdbd11d644214ca5601536e9aeb26882f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-11-16 23:09:11 +00:00
Simon Glass d3870a2761 ec/google/chromeec: Update ec_cmd_api.h and ec_commands.h
Generated using update_ec_headers.sh [EC-DIR].

The original include/ec_commands.h version in the EC repo is:
  ab9b64ac4c Add a host command to print info about AP-firmware state
The original include/ec_cmd_api.h version in the EC repo is:
  ab9b64ac4c Add a host command to print info about AP-firmware state

BUG=b:300525571
BRANCH=none
TEST=none

Change-Id: I3570e073a91621cb1d28a24aa35c1f4beedceaab
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79066
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16 23:08:06 +00:00
CoolStar 42be899b65 acpi/device: Only return dev->ops->acpi_name if non-NULL
Returning a NULL device name can cause issues if something else does
handle it.

E.g. UART and GNA devices on Intel Alder Lake-N cause
INTERNAL_POWER_ERROR BSOD's in Windows when enabled due to invalid
packages being created from a NULL name

Test: build/boot google/nissa (craaskvin) to Win11

Change-Id: I0679147ad3e330d706bbf97c30bc11b2432e2e8a
Signed-off-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-11-16 22:18:25 +00:00
Matt DeVillier 31327d8b4b mb/google/skyrim/frostflow: Drop GPIO override for camera shutter
Appears to not be used under Windows, Linux, or ChromeOS, and causes
high CPU usage at idle under Windows.

BUG=none
TEST=build/boot Win11, Linux on google/frostflow, verify camera shutter
function unchanged, CPU usage under Windows idles where expected.

Change-Id: I8a6ea3b886766bdb055b40949c75bec0264eecc5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-16 18:11:25 +00:00
Felix Singer 26e7c1eae4 Revert "tests: Allow specifying vboot source directory"
This reverts commit 7713a2f295.

Reason for revert: breaks main branch

Change-Id: I2749bea9369c222e510b838e278c7797d5dce56e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78852
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
2023-11-16 16:10:26 +00:00
Matt DeVillier 7739e53398 Update amd_blobs submodule to upstream main branch
Updating from commit id edd465837e26 (2023-10-20):
  cezanne: Update PSP binaries to release 0.11.11.75

to commit id e4519efca746 (2023-11-15):
  Revert "picasso: Update PSP binaries to release 0.8.13.7B"

This brings in 1 new commit:
e4519efca7 Revert "picasso: Update PSP binaries to release 0.8.13.7B"

Change-Id: I860aa04324128199cbc91a5f310fcdf92a2cd65d
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-16 16:01:40 +00:00
Matt Parnell 84e8037a43 mb/system76/rpl: Allow 5600 MT/s memory for RPL-HX
System76 only sells units with memory speeds up to 5200 MT/s, but the
i9-13900HX supports up to 5600 MT/s memory.

Tested by running memtest and checking dmidecode reports 5600 MT/s when
using 2x16 GB 5600 MT/s Crucial SODIMMs (CT2K16G56C46S5) on addw3,
bonw15, serw13.

Change-Id: I9bb0435769c70c1db06d2c5cca2dd28eb5331f49
Signed-off-by: Matt Parnell <mparnell@gmail.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Tested-by: Levi Portenier <levi@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78912
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16 14:44:14 +00:00
Felix Singer a03999be25 mb/supermicro/x11: Make use of chipset devicetree
Use the references from the chipset devicetree as this makes the
comments superfluous and remove devices which are turned off.

Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78594
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16 13:19:16 +00:00
roccochen@chromium.com 7713a2f295 tests: Allow specifying vboot source directory
Respect VBOOT_SOURCE while including generic headers.

BUG=none
TEST=make clean-unit-tests &&
     VBOOT_SOURCE=/path/to/vboot_reference/ make unit-tests -j
TEST=make clean-unit-tests && make unit-tests -j
BRANCH=none

Change-Id: Id3bb3726c91167d2dd648d748763a3948787f28d
Signed-off-by: roccochen@chromium.com <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78849
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16 12:55:23 +00:00
Ruihai Zhou 94a2d74926 mb/google/geralt: Disable SD card support for Ciri
According to proto schematics, the SD card is removed.

BUG=b:308968270
TEST=emerge-geralt coreboot
BRANCH=None

Change-Id: Id4e021e7896d093560f39c40573ac616d76438c2
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
2023-11-16 12:04:30 +00:00
Ruihai Zhou d3089a36d5 mb/google/geralt: Move backlight-related functions to common panel.c
These backlight related functions can be reused in other variants, move
them out to the panel.c. Also the panel_geralt.c should be used for
Geralt, enable it on Geralt board only.

BUG=b:308968270
TEST=emerge-geralt coreboot
BRANCH=None

Change-Id: I5d4035d5f480551c428c450826e23bf77f2fe08a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78955
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2023-11-16 12:04:07 +00:00
Maximilian Brune 77eaec6587 lib/device_tree.c: Fix print_property
This uses the size attribute to traverse the possible string.
This patch traverses the entire property for non printable characters
and not just until the first 0 is hit.

Now numbers that start with a zero (memory wise) are not falsely
recognized as strings:

before the patch:
clock-frequency = "";

after the patch:
clock-frequency = < 0x1c2000 >;

Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I229c07b76468fe54f90fa9df12f103d7c7c2859d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-16 12:01:40 +00:00
Tyler Wang f7f661f375 drivers: spi_flash: Add space before colon to fix coding style
BUG=none
TEST=build karis firmware pass

Change-Id: I67b4ca4c8fde795d4206eaa0b9ea9d9bfc768ac6
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-16 11:59:20 +00:00
Ruihai Zhou e6411c0a55 mb/google/geralt: Create variant Ciri
Create the variant Ciri and enable MAX98390 AMP for it. The panel
related support will be added in the follow up CLs.

BUG=b:308968270
TEST=emerge-geralt coreboot
BRANCH=None

Change-Id: I7bbe9ed5e722a70bab1c799a61ce38d2ad58ab25
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78954
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-16 09:25:18 +00:00
Usha P 45b1b7bf4d mb/intel/mtlrvp: Create mtlrvp4es_p_ext_ec variant
This patch creates a new variant mtlrvp4es_p_ext_ec. The new
variant will support ESx samples. The existing mtlrvp_p_ext_ec
variant will support the QS samples.

BUG=b:310775573
TEST= Build and boot mtlrvp4es_p_ext_ec.

Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Iad72c0f6343af149d16d8b1f8639ba496f6aab0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-16 08:20:00 +00:00
Subrata Banik 7f7ebb7b3d lib: Update locales for non-VBOOT platforms
This patch sets the default locales to English for platforms that
do not have support for VBOOT configuration. This ensures that the
system will use English locales if the platform does not provide
its own locale settings.

TEST=Built and booted the google/rex platform successfully.

Change-Id: I7554c8bfd58411f460deeb22cf7218059ca8ba9f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79054
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-16 05:19:20 +00:00
Subrata Banik 2495f24bd7 tests/lib: Enforce ux_locales-test with CONFIG_VBOOT
The ux_locales-test relies on the ability to determine supported
locales for the platform. However, this information is unavailable
without VBOOT config being enabled. Therefore, enforce this test for
platforms with VBOOT config alone to avoid unnecessary failures.

Change-Id: I2828eb062e2b601e073e7dab9aef7316fc6ba2cd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hsuan-ting Chen <roccochen@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-11-16 05:18:47 +00:00
David Wu 0e11284b21 mb/google/brya/var/osiris: Update power limit values for RPL CPU
Update power limit values based on the suggestion of the thermal
team for RPL CPU.

The PL1 value (28W) suggested by the thermal team which is different from the reference document 686872 (PL1=15W).

BUG=b:310834985
TEST=built and booted into OS.

Change-Id: Ia2540ecd1fc453701b9160c97d82ba50b88ee848
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79059
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16 02:35:12 +00:00
Felix Held 09b7dc51ce acpi/acpigen: drop len assert in acpigen_pop_len
This is already handled as a separate case in the code below, so there's
no need for this assert any more.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7511ec5683a924dc289faa2b9fabd0e8714d291e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-15 13:53:09 +00:00
Felix Held 575ee135d1 acpi/acpigen: introduce and use ACPIGEN_RSVD_PKGLEN_BYTES
Use a define instead of magic numbers.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2c6d17bd78a0e207f9130102b43ba78aa55ce377
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2023-11-15 13:52:59 +00:00