Move the verb table to variant directory to allow for different tables
for different variants.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4260188057d1c3b4e6ea7c82f085fad0cc244881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Support was created for the NPCE9m5x series, using version 1.1
of the datasheet. The specific model tested was the NPCE985P/G,
on the StarLite Mk IV with version 1.00 of the EC firmware.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib66baf1e88f5d548ce955dffa00c9b88255b2f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Rather than using `ite_`, use `ec_` so the same functions
can be called for different ECs.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie61af233f731eb47772af1c82c6abdc515bc89cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Only Cr50 versions starting at 0.5.5 support long IRQ pulses, so this
feature is enabled based on the value of the board_cfg register (see
CB:61722).
However, Ti50 versions below 0.0.15 don't support the board_cfg
register, and trying to access it will cause I2C errors (see CB:63011).
Also, all Ti50 versions only support long IRQ pulses. Therefore, add a
workaround to force enable long IRQ pulses for boards using Ti50
versions under 0.0.15, instead of enabling it based on board_cfg. This
workaround will be removed once all Ti50 stocks are updated to 0.0.15 or
higher.
BUG=b:225941781
TEST=Boot nivviks and nereid to OS with Ti50 0.0.14 and check there are
none of these I2C errors:
[ERROR] I2C stop bit not received
[ERROR] cr50_i2c_read: Address write failed
[ERROR] cr50_i2c_tis_status: Failed to read status
Change-Id: Iaba71461d8ec79e8d6efddbd505339cdf1176485
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63160
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move WWAN power on sequence from OS to coreboot. This can save the
WWAN initial time about 10S. Another purpose is power resource be
removed because we don't power off the LTE in S0ix.
BUG=b:223490884
TEST=FM101-GL work as expected.
Enumerate time from
[ 17.747145] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd
[ 17.760192] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04
[ 17.760210] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 17.760215] usb 4-2: Product: Fibocom FM101-GL Module
[ 17.760220] usb 4-2: Manufacturer: Fibocom Wireless Inc.
[ 17.760224] usb 4-2: SerialNumber: 9c88998f
to
[ 3.936409] usb 4-2: new SuperSpeed USB device number 2 using xhci_hcd
[ 3.966695] usb 4-2: New USB device found, idVendor=2cb7, idProduct=01a2, bcdDevice= 5.04
[ 3.989989] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
[ 4.003813] usb 4-2: Product: Fibocom FM101-GL Module
[ 4.019760] usb 4-2: Manufacturer: Fibocom Wireless Inc.
[ 4.019762] usb 4-2: SerialNumber: 9c88998f
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I0f3fe999ae3a109b739629948b619a389a9059b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
The patch deselects ALDERLAKE_A0_CONFIGURE_PMC_DESCRIPTOR Kconfig for
ADL RVP board. The flag updates PMC settings in the IFD for Alder Lake
A0 silicon. As Alder Lake A0 is intermediate stepping, and the IFD is
locked in the production systems, so the Kconfig is deselected.
TEST=Build the coreboot for adlrvp
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I966be42ba662861f4a6933d7275ecc13860220f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch fixes the table issue in markdown file identified with commit
96481066 (Documentation: gpio: Update table as per coreboot guidelines).
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ifd8265b92b5ef0dcabb754371591477ca19c39be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
coreboot.pre doesn't follow the standard Make conventions. It gets
modified by multiple rules, and thus we can't compute the dependencies
correctly. This means we need to manually delete it before starting the
dependency calculations.
i.e., Building firmware with the seabios payload now works correctly.
Fixes: dd6efce934 ("Makefile: Add .SECONDARY")
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If5fa3f0b8d314369a044658e452bd75bc7709397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Only enable the PCIe root ports that have corresponding DXIO descriptors
and also update the comments to have them match the actual hardware
configuration.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I378c620abb6e52de680669b6edd228874153e399
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63162
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the DXIO descriptors to match the default PCIe lane mapping on
the chausie board. With this configuration and a board-level rework to
bypass the EC control of the NVMe SSD power supply rail, this
configuration results in the SSD being detected on the root port on bus
0 device 2 function 3 and usable as boot device. This was also validated
against the schematics revision B.
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib74988b741f748d240ef09fa0dba8885bdc5e706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63161
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow the Moli GPIO Table_20220324.xlsx to update it.
1.Set A15 as the default value.
2.Set A14, A19 NC.
3.Set C3, C4 as the default value.
4.Set D9 as the default value.
5.Set E5, E13 as the default value.
6.Set R4, R5 as the default value.
7.Update E14.
8.Set E12 as the default value.
9.Set D16 as the default value.
BUG=b:220821454
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ia54256244111a99cb130b74f78c37815099a021a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
While adding this train of patches to program the dGPU power sequences,
I noticed some of the GPU GPIOs are incorrectly programmed in ramstage,
so this patch fixes the settings.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I622b1f5cfba84727bb31792358ca4162c7fa9f52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Clang is unhappy about codepath of an invalid parameter because
variables remain unset.
Change-Id: I1ba392a48cf3f81a29d9645e5cf220b122d588af
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch adds an option to disable loglevel prefixes. This patch helps
to achieve clear messages when low loglevel is used and very few
messages are displayed on a terminal. This option also allows to
maintain compatibility with log readers and continuous integration
systems that depend on fixed log content.
If the code contains:
printk(BIOS_DEBUG, "This is a debug message!\n")
it will show as:
[DEBUG] This is a debug message!
but if the Kconfig contains:
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=n
the same message will show up as
This is a debug message!
Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com>
Change-Id: I911bb601cf1933a4c6498b2ae1e4cb4d4bc85621
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
ESPI is not initialized in PSP. Hence any attempt to write to port80
causes failure to boot. Disable PSP postcodes for now and re-enable it
later after ESPI is initialized in PSP.
BUG=b:224618411
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is done to work around a hang when SMU writes to port80. Remove it
after the issue is fixed.
BUG=b:224618411
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63122
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the PCIe CEM specification, the deassertion of PERST#
should occur at least 100ms after the assertion. To ensure the 100ms
delay requirement is met, calculate the elapsed time since assertion. If
it is smaller than 100ms, do an extra delay.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the measured PERST# time:
[DEBUG] mtk_pcie_domain_enable: 432517 us elapsed since assert PERST#
[INFO ] mtk_pcie_domain_enable: PCIe link up success (17 tries)
And the SSD information in boot log is as follows:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be
delayed 100ms (TPVPERL) for the power and clock to become stable.
Instead of asserting PERST# right before PCIe initialization and waiting
for 100ms, which is currently the only function of 'mtk_pcie_pre_init',
so that the extra 100ms delay in ramstage is avoided.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add early init support for MT8195 platform.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I4eb7da53ff76c385cab18bbf84970e96b61662ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add support for "early_init_data" region, which can be used to store
data initialized in an early stage (such as bootblock), and retrieve it
in later stages (such as ramstage).
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
BRANCH=cherry
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
SMU locks up sometimes if the port80 enable bit is cleared in the ESPI
Decode register. Add a config to choose between clearing the entire ESPI
Decode Register vs retaining the port80 enable bit.
BUG=None
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Configure GPIO according to b:224107199 comment#15.
- GPP_E19 from NF to NC.
BUG=b:224107199
TEST=emerge-brya coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I06d02c5a8b6cf65d5643eaf30fb277c3321dac8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
The feature "USE_CBMEM_DRAM_INFO" is supported in MT8186.
Therefore, we select this configuration to enable it.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ieaaf57aaee79c9dce69cc1acaa092207f0f906de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63114
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The memory initialization reference code didn't support returning
DRAM information in the old platforms, for example MT8192 and MT8195.
So we have to add a new configuration USE_CBMEM_DRAM_INFO to make
sure the common code will try to get DRAM information on new
platforms supporting that.
BUG=none
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iebe9ea0c1d01890b09fdf586813d85adde9702e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The current pmif register setting for low power mode is incorrect,
which is causing suspend failure. The issue of suspend failure is that
SRCLKENA0 will not be pulled down. EC will not be informed AP is
suspending now becuase of this. Therefore, add pmif_spmi_set_lp_mode()
to correct the setting.
This implementation is based on chapter 3.7 in MT8186 Functional
Specification.
BUG=b:215639203
TEST=test of suspend and resume pass.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Change-Id: I2d02198f19f9cb052fba612c02404a6af1a10adb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The Cherry follower projects may choose Max98390 for audio output
so we have to add a new config CHERRY_USE_MAX98390. Also, the
'dojo' device is the first one to use it.
BUG=b:204391159
BRANCH=cherry
TEST=emerge-cherry coreboot
TEST=Verify beep function through CLI in depthcharge successfully
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63083
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch moves `pmc_clear_pmcon_sts` function into common code and
remove SoC specific instances.
Accessing PMC GEN_PMCON_A register differs between different Intel
chipsets. Typically, there are two possible ways to perform GEN_PMCON_A
register programming (like `pmc_clear_pmcon_sts()`) as:
1. Using PCI configuration space when GEN_PMCON_A is a PCI configuration
register.
2. Using MMIO access when GEN_PMCON_A is a memory mapped register.
SoC users to select `SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION` Kconfig to
perform GEN_PMCON_A register programming using PMC MMIO.
BUG=b:211954778
TEST=Able to build brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeff Daly <jeffd@silicom-usa.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The Sabrina microcode update files are 3200 bytes large and not 5568
like it is the case on Cezanne where this file was originally copied
from.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I12209d523096781195ba8957ec797d8c80eecbe5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This will setup the eSPI GPIOs in bootblock right before eSPI init.
BUG=b:226635441
TEST=build skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ff32bf840aa4b757e98d876cbd4e2ba15a760da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The eSPI CS function only exists on AGPIO30.
We will need to rework all boards to make eSPI function.
I also fixed the comments on the other eSPI pins.
BUG=b:226635441
TEST=Build skyrim
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib03c0a7dcad31d10dd4bad0d10a0184ab84aef9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Although coreboot can allocate resources above 4G, Linux does not
consider those allocation valid when there is no region above 4G in
_CRS and disables the device.
TESTED: x220 with and external GPU via the expresscard slot. Linux
does not touch the BARs allocated above 4G.
Change-Id: If1be9a2c1e03e5465fd3b164469511eca60edc5a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Regarding JEDEC Standard No. 21-C, Release 30, page 13, DDR4_SPD_72B_SO_RDIMM
and DDR4_SPD_72B_SO_UDIMM values are respectively 0x08 and 0x09.
There is no affected board in coreboot tree.
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Id4e9c3814e2e7f379917bf93f7975af3aad31dbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This patch uses the FSP event handler feature and updates with coreboot
native debug implementation to unify the debug library between coreboot
and FSP.
BUG=b:225544587
TEST=Able to build and boot Brya with the same FSP debug log before and
with this code changes.
Before:
Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
The 0th FV start address is 0x000F961B000, size is 0x00150000, handle is 0xF961B000
Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
With this code change:
[SPEW ] Register PPI Notify: DCD0BE23-9586-40F4-B643-06522CED4EDE
[SPEW ] Install PPI: 8C8CE578-8A3D-4F1C-9935-896185C32DD3
[SPEW ] Install PPI: 5473C07A-3DCB-4DCA-BD6F-1E9689E7349A
[SPEW ] The 0th FV start address is 0x000F95C0000, size is 0x00160000, handle is 0xF95C0000
[SPEW ] Register PPI Notify: 49EDB1C1-BF21-4761-BB12-EB0031AABB39
[SPEW ] Register PPI Notify: EA7CA24B-DED5-4DAD-A389-BF827E8F9B38
[SPEW ] Install PPI: B9E0ABFE-5979-4914-977F-6DEE78C278A6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a0530a282657e379a00c3e7d0ed8148dd5e9196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch assigns FSP handler event for FSP-M and FSP-S with coreboot
romstage and ramstage debug handler when FSP_USES_CB_DEBUG_EVENT_HANDLER
Kconfig is enabled.
BUG=b:225544587
TEST=Able to build and boot brya. Also, verified the FSP debug log is
exactly same before and with this code change.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I665def977faaae45f6f834d75e8456859093ba49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Without setting the set_resources field for pciexp_hotplug_dummy_ops,
we will get an error during pciexp_hotplug_dummy.
[ERROR] NONE missing set_resources
Because the set_resources field is considered mandatory, explicitly set
it as no-op noop_set_resources.
BUG=b:220639445
TEST=emerge-brya coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ifee7479c69cf16025dbd4e3924056ed7f8e253cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63101
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Skyrim DXIO descriptors using info from AMD and skyrim bouard
shematics.
BUG=b:225179599
TEST=Boots to OS on Skyrim Board
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Implement the GPIOs that have been changed from genesis.
- Connect scaler UART on pins C12/C13
- Connect the HDMI redriver I2C on C18/C19
- Connect the iMX8 signals on D1/D2/D3/D21/D22
- Connect the EC interrupt on D14 (same as on scout)
- Connect PCH_TYPEC_UPFB on E15 (same as on genesis)
- Configure as not connected the following unused pins: D23, E11, E12,
F11 -> F22, H0, H8, H9
BUG=b:200876872
TEST=moonbuggy boots
Change-Id: Ie9cafe81e391bce6ab7ffbe23c2d57b407d146f3
Signed-off-by: Pablo Ceballos <pceballos@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Using the GPP_F22 as mic mute switch based on the latest schematic.
BUG=b:223737606, b:216110896
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
The mic_mute event is changed when the mic_mute GPIO pin is switched.
Event: time 1647939954.639995, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 0
Event: time 1647939954.639995, -------------- SYN_REPORT ------------
Event: time 1647939954.648152, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 1
Event: time 1647939954.648152, -------------- SYN_REPORT ------------
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Currently, we control the GPP_D0 in the flash_fp_mcu in order to
program the component's firmware. If we set this pin to NC, then we
can't control the GPP_D0 output low/high and that make the system fails
to program the component's firmware. This patch sets the GPP_D0 to GPO
to fix it.
BUG=b:204679292
BRANCH=firmware-brya-14505.B
TEST=program the component's firmware
Change-Id: I2f58c324f807a067dbe338f044a33dc9622ca469
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Sean Rhodes