Commit graph

2051 commits

Author SHA1 Message Date
Felix Held
0c5885cd94 soc/amd/common/include/lpc: add definitions for LPC LDRQ control bits
The definitions of bit 9 and 10 somehow got swapped between Picasso and
Renoir/Cezanne, so put those in the Cezanne-specific header file. The
reference code writes the same values to the raw bits in both, so we
probably would still get away with putting this into the common header,
but it's better to keep the defines consistent with the documentation in
all cases.

Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03
and cross-checked to be compatible with the Picasso PPR #55570 Rev 3.16.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a033d63eeb06eed6783e4c3797ad8dea490db8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11 15:15:27 +00:00
Raul E Rangel
968f140ecb Revert "soc/amd/cezanne: Disable Co-op multitasking"
This reverts commit 5f80e7c764.

The smm_do_relocation failure has been fixed. I also added CPU_INFO_V2
into this patch to satisfy the dependency.

BUG=b:194391185, b:179699789
TEST=reboot stress test guybrush for 50 iterations.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I134c14748711a9c9865e0cc3e3185825f85248ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-05 22:39:38 +00:00
Martin Roth
26f97f9532 src/soc to src/superio: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-05 18:07:08 +00:00
Felix Held
9f17fa33f9 soc/amd/cezanne/early_fch: move mb_set_up_early_espi into if block
mb_set_up_early_espi should only be called when
SOC_AMD_COMMON_BLOCK_USE_ESPI is selected.

TEST=None

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic8ad724a2a79c1995fbe9d97f11a0f69eed9435c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-27 13:40:34 +00:00
Karthikeyan Ramasubramanian
1140b7cc72 soc/amd/cezanne: Enable CCP DMA
Enable CCP DMA use in PSP verstage. This helps to reduce the boot time.

BUG=b:194990811
TEST=Build and boot to OS in Guybrush. Observed a 35 - 40 ms improvement
in the boot time.

Before CCP DMA:
 508:finished loading body                             898,286 (287,576)
Total Time: 2,146,182

After CCP DMA:
 508:finished loading body                             853,627 (240,061)
Total Time: 2,110,117

Cq-Depend: chrome-internal:4116566
Change-Id: I6e4f081622a2ec78763adf56548204efc1bccf39
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-27 13:40:10 +00:00
Karthikeyan Ramasubramanian
c2f6f35b3a soc/amd/common/psp_verstage: Introduce boot device driver
PSP verstage can access the boot device either in Programmed I/O mode or
DMA mode. Introduce a boot device driver and use the appropriate mode
based on the SoC support.

BUG=b:194990811
TEST=Build and boot to OS in Guybrush.

Change-Id: I8ca5290156199548916852e48f4e11de7cb886fb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57563
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-27 13:40:03 +00:00
Karthikeyan Ramasubramanian
b3ffff87dd soc/amd/cezanne, vc/amd/fsp/*: Add support for CCP DMA SVC call
Add support to access the boot device from PSP through Crypto
Co-Processor (CCP) DMA. Implement a SVC call to use CCP DMA on SoCs
where it is supported and a stub on SoCs where it is not supported. This
provides an improved performance while accessing the boot device and
reduces the boot time by ~45 ms.

BUG=b:194990811
TEST=Build and boot to OS in guybrush. Perform cold and warm reboot
cycling for 250 iterations.

Change-Id: I02b94a842190ac4dcf45ff2d846b8665f06a9c75
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-27 13:29:37 +00:00
Felix Held
07958d3e86 soc/amd/common/block/include/acpimmio_map: add AOAC acronym in comment
The Always On Always Connected block is referenced as AOAC in the code,
so add that acronym in the comment and change the "Connect" to
"Connected".

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6a23e0ccff62c6ceddae70e1bef5c5abf872c495
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-27 13:20:33 +00:00
Felix Held
5ef5873576 soc/amd/common: factor out FSP-related parts of common Kconfig
TEST=Timeless build for Mandolin results in identical image.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2fb6c29b9f42c00f252994ae2a40b7ff668105a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24 15:48:24 +00:00
Felix Held
c9737c5ce9 soc/amd/common: move block/pi out of the block folder
Since the binaryPI glue code is specific to a binary interface, but not
for a hardware block, move it out of the common blocks directory. This
also brings the binaryPI support in line with the FSP support which is
used on the newer generations. This also drops the
SOC_AMD_COMMON_BLOCK_PI Kconfig option and makes use of the already
existing SOC_AMD_PI Kconfig option instead.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I014e538f2772938031950475e456cc40dd05d74c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24 15:47:59 +00:00
Felix Held
c0982abf86 soc/amd/common/block: move binaryPI S3 block into PI block
The code in soc/amd/common/block/s3 is specific to the AMD binaryPI
coreboot integration, so move the code to soc/amd/common/block/pi. This
drops the SOC_AMD_COMMON_BLOCK_S3 Kconfig option and integrates the
dependencies and selections into the SOC_AMD_COMMON_BLOCK_PI Kconfig
option. Since only selecting SOC_AMD_COMMON_BLOCK_PI but not
SOC_AMD_COMMON_BLOCK_S3 resulted in missing functions in the linking
process, we don't lose support for any working configuration by only
having one Kconfig option for both parts.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib2bd99a88d8b05216688bc45d9c4f23a007ce870
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24 15:47:44 +00:00
Felix Held
dea4e0fe68 soc/amd/common/blocks/include: rename gpio_banks.h to gpio.h
This brings the AMD SoC GPIO code in line with the Intel SoC code and
removes the not really needed suffix.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23 18:33:00 +00:00
Felix Held
2876e4f49a soc/amd/common/blocks: rename gpio_banks folder to gpio
This brings the AMD SoC GPIO code in line with the Intel SoC code and
removes the not really needed suffix.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3dfcca2f126eb49c962b5cc32cbcf72e04f3f170
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23 18:31:53 +00:00
Felix Held
7011fa1135 soc/amd: rename program_gpios to gpio_configure_pads
Use the same function name as in soc/intel for this functionality. This
also brings the function name more in line with the extended version of
this function gpio_configure_pads_with_override which additionally
supports passing a GPIO override configuration.

This might cause some pain for out-of-tree boards, but at some point
this should be made more consistent, so I don't see a too strong reason
not to do this.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23 14:42:03 +00:00
Felix Held
05df6ec844 soc/amd,intel/common/include/gpio: improve documentation of overrides
Explicitly point out that gpio_configure_pads_with_override will ignore
GPIOs that are only in the override configuration, but not in the base
configuration.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1bdfcac89b81fef773938133a2699897c6ee9415
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-23 14:41:30 +00:00
Felix Held
f7f1f1672f soc/amd/common/block/gpio_banks: Rework GPIO pad configuration
Before this patch, gpio_configure_pads_with_override called
program_gpios once for each GPIO that needed to be configured which
resulted in base_num_pads - 1 unneeded master_switch_set/
master_switch_clr sequences for the gpio_configure_pads_with_override
call. Instead implement gpio_configure_pads_with_override as the more
generic function and program_gpios as a special case of that which
passes an empty override configuration and override pad number to
gpio_configure_pads_with_override.

TEST=GPIO configuration and multiplexer register values are the same for
all GPIOs on google/guybrush right before jumping to the payload before
and after the patch.

Change-Id: Ia8e47b2a278a1887db5406c1f863ddafa6a68675
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-22 15:54:52 +00:00
Felix Held
16ae682cb9 soc/amd/common/block/gpio_banks: add missing types.h include
In this file bool, uint8_t and uint32_t are used, so include types.h
directly to have those types defined instead of relying to have those
included indirectly via amdblocks/gpio_banks.h.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6f4626a50219fab818e8bc5087961a731b44e71b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-21 20:22:54 +00:00
Felix Held
bc0032a8c2 soc/amd/picasso/fsp_m_params: use DEV_PTR to check if device is enabled
The aliases are defined in the chipset devicetree, so the device
pointers will be available for all boards using this SoC.

TEST=None

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id4c921575e978bb29e61f35e78ff2a1711acf06a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-21 13:56:32 +00:00
Felix Held
a0b2510357 soc/amd/cezanne/fsp_m_params: use DEV_PTR to check if device is enabled
The aliases are defined in the chipset devicetree, so the device
pointers will be available for all boards using this SoC.

TEST=None

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id655e9eba9b8e9898fa01bf03876074e136cc7c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-21 13:56:26 +00:00
Julian Schroeder
f9080ce6d9 soc/amd/cezanna/acpi/mmio.asl: enable ACPI AOAC for I2C
This enables runtime power management for the I2C controllers.

BUG=b:182556027, b:183983959
TEST=enable dynamic debug in kernel and check i2c D3/D0 transitions
during suspend_stress_test.

Change-Id: Ia6b9ca95d751f32b7cd701494377f15091c22d2f
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56462
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-20 12:56:21 +00:00
Felix Held
d453208623 soc/amd/cezanne/acpi/mmio: uncomment AOAC_DEVICE macro for UARTs
This enables runtime power management for the UART controllers.

BUG=b:183983959

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e57d6312feda459cec65f330c6d2072774d4eb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-20 12:50:01 +00:00
Felix Held
5340abcd2f soc/amd/common/block/pi/image: replace stdbool.h include with types.h
Apart from the bool type, uint8_t, uint32_t and uint64_t are used in
this file, so include types.h instead of stdbool.h.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I30088d68132058f40b974fbaa822f322b58ed6c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17 20:27:42 +00:00
Felix Held
779eeb2fb5 soc/amd/picasso/Kconfig: increase FSP_M_SIZE
When using a debug build of the FSP, the FSP-M binary is larger than the
memory region we have allocated for it, so increase the size to make the
binary of the debug build fit in there. Also adjust the VERSTAGE_ADDR so
that it starts right after the the FSP-M memory region.

TEST=coreboot builds now successfully when using a debug version of the
FSP

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib64806bcf948d5ed4bcf8e1f50004091f125dc7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17 17:14:28 +00:00
Raul E Rangel
aa1b67de29 soc/amd/common/block/pi: Add missing include stdbool.h
BUG=b:179699789
TEST=build morphius

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I298ce1ee436a5c8eb8375dc5fe55665bbf977463
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-16 18:39:03 +00:00
Raul E Rangel
4969b4d955 soc/amd/picasso/agesa_acpi: Add missing include 'arch/cpu.h'
Needed for cpuid_ext.

BUG=b:179699789
TEST=build morphius

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib3a132bea06443ee4c1501b1c746400c541fd805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-16 18:37:55 +00:00
Tim Wawrzynczak
84428f72d0 drivers/intel/fsp2_0: Pass orientation to fsp_report_framebuffer_info
Instead of always passing LB_FB_ORIENTATION_NORMAL, allow the chipsets
implementing the callback to pass in an orientation.

BUG=b:194967458
BRANCH=dedede

Change-Id: I4aacab9449930a75aca9d68bf30d019f86035405
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-16 00:09:36 +00:00
Raul E Rangel
b0be267c44 soc/amd/common/block/cpu: Add missing include
We use cpuid_eax to get the cpuid family.

BUG=b:179699789
TEST=build guybrush

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib73e66241bb0cfd99a035c217c527338aa2d0e4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-13 14:17:15 +00:00
Karthikeyan Ramasubramanian
2c59a3884d Revert "soc/amd/common: Skip psp_verstage on S0i3 resume"
This reverts commit b90e6fdd25. Latest
releases of PSP does not load PSP verstage on S0i3 resume. Hence no need
to skip PSP verstage on S0i3 resume.

BUG=b:196400450
TEST=Build and boot to OS in Guybrush. Trigger a suspend/resume cycle
and then a reboot and ensure that the system boots to OS.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Iaeb92edb69662e6c06f4d0e3d7b760d4597bf650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-09 20:41:31 +00:00
Felix Held
f4e6466924 soc/amd/cezanne/include/gpio: add remote GPIO pin mux definitions
Add the pin definitions for the remote GPIOs and the GPIO pin mux values
for the GPIO mode of those pins. For now, accessing the remote GPIOs is
only supported from the native coreboot code running on the x86 cores
and not from verstage on PSP or ACPI.

BUG=b:194524995
TEST=On Majolica with a Cezanne APU configuring GPIO 262 as output and
then toggling that GPIO in an infinite loop in the mainboard's bootblock
code results in GPIO 262 toggling as expected.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0e57042e74da88503b36d6065e9500876287f8bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-09 17:49:48 +00:00
Felix Held
7110235902 soc/amd/common/block/acpi/gpio: add warning for remote GPIO usage
Right now the ACPI code doesn't support accessing the remote GPIO block
yet, so don't generate invalid remote GPIO access functions and warn
about those being unsupported.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id364a59c9650bf4e3633b494b01ab23c0bbc50b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-09-09 17:49:23 +00:00
Felix Held
b4fe8c5948 soc/amd/common/block/gpio_banks: add remote GPIO support
Some AMD SoCs have a 5th GPIO bank, the remote GPIO bank, which isn't
located right after the 4th GPIO bank, but instead at a different
location inside the APCIMMIO region. A difference to the first 4 GPIO
banks is that the corresponding GPIO MUX registers aren't in a separate
bank, but at the end of the remote GPIO region. So this remote GPIO
region only supports 48 GPIOs with a 32 bit configuration register each
and has the 8 bit GPIO MUX registers beginning at offset 0xc0 in the
remote GPIO region.

For now using the remote GPIOs from verstage on PSP isn't supported. To
support this, it would need to map acpimmio_remote_gpio and update the
pointer like it already does for acpimmio_gpio0, acpimmio_iomux and a
few others.

BUG=b:194524995

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic8d7ff677a99381a5558782b80b0c4cae67602db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-09 17:49:11 +00:00
Felix Held
467eb569c0 soc/amd/common/block/acpimmio: add remote GPIO bank ACPIMMIO region
Currently coreboot for the AMD SOCs only supports accessing the up to 4
main GPIO banks of up to 64 GPIOs each. Some AMD SoCs including Cezanne
have another GPIO bank in the ACPIMMIO region that can contain up to 48
GPIOs beginning with GPIO 256 which is called the remote GPIO bank. The
first 48 DWORDs of that ACPIMMIO bank are the 32 bit wide GPIO registers
and beginning at offset 0xc0 it has the corresponding 8 bit wide GPIO
MUX registers.

BUG=b:194524995

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice4e3358de17ac2601621814978cdb70e6f2c926
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-09 14:20:55 +00:00
Felix Held
7bbde76014 soc/amd/common/block/include/i2c: introduce I2C_RESET_SCL_PIN macro
Add and use the I2C_RESET_SCL_PIN macro for populating the i2c_scl_pins
array that is used for the sb_reset_i2c_peripherals call to bring the
I2C buses into a defined state.

TEST=Timeless build results in identical image for Mandolin.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifedc09d0bf745545fa0510df7d5037f02b9012a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-09 14:20:35 +00:00
Julian Schroeder
4671983401 soc/amd/cezanne/fsp_m_params: set usb_phy version and length.
Setting the usb_phy version and length in the soc code instead of devicetree.
That way the devicetree code does not have to reapeat it for different
AMD Cezanne based systems.

Tested on guybrush by changing phy settings in devicetree and then checking
the usb phy register.

Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I2db49e095672054b9b15042fb003a93b67e3a4c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-08 20:45:33 +00:00
Angel Pons
44985ae757 cpu/x86/tsc: Deduplicate Makefile logic
The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc`
is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig
option is enabled.

Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and
drop the now-redundant inclusions from platform code. Also, deduplicate
the `UDELAY_TSC` guards.

Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08 14:35:16 +00:00
Felix Held
8b7600058f soc/amd/common/block/gpio_banks: add comment about acpimmio_* symbols
Suggested-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0016a6c7d6581cb261cab6178268c1a86b89c839
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56831
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08 00:17:23 +00:00
Felix Held
b7f056307d soc/amd/common/block/gpio_banks: inline iomux_read8 and iomux_write8
Since both functions are only called from one function each, inline them
into those functions. Also get_gpio_mux just returned the return value
of iomux_read8, so there were two functions with identical functionality
which shouldn't be the case.

Suggested-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5662d0226edb25a9954fa47b42e208729a79e5a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56830
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08 00:17:14 +00:00
Felix Held
aa9ad05449 soc/amd/common/block/gpio_banks: factor out gpio_mux_ptr
This aligns the GPIO MUX access more with the GPIO control register
access and will facilitate adding support for the remote GPIO bank. Also
change the GPIO number argument type to gpio_t.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4054656c5cc23ea942e8dd370fbbffca304755d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-08 00:16:53 +00:00
Felix Held
85e733f0ef soc/amd/common/include/acpimmio: reduce visibility of GPIO MMIO access
Introduce amdblocks/acpimmio_legacy_gpio100.h so that the old pre-SoC
chipsets can still access the raw GPIO100 and IOMUX ACPIMMIO registers
while only allowing GPIO accesses through the GPIO API on the SoCs.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18872dfa40d53ba8b0d7802eec52ede5e2ae617a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-08 00:16:37 +00:00
Felix Held
ad38ac0182 soc/amd/common/block/gpio_banks: move GPIO MUX access functions
Move those two functions near the top of the file to have all functions
that do the hardware accesses in one place.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If787e6e1d124a932beafd73e5ce7d0ce4869e800
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-08 00:16:16 +00:00
Felix Held
afa750bf57 soc/amd/common/block/gpio_banks/gpio: use unsigned types where needed
Use unsigned integers for variables that aren't supposed to become
negative.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5ee037221b9818b0474fe0376323e522c1b3b516
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-09-08 00:15:59 +00:00
Felix Held
d0911e94dd soc/amd/common/block/gpio_banks/gpio: use gpio_t for GPIO numbers
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7cf9cbd2a287dcfe3a47a8a6b164c2b3d8ae95d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-08 00:15:46 +00:00
Felix Held
f5658cf1a5 soc/amd/common: move GPIO ACPIMMIO access functions to gpio_banks block
Since the raw GPIO MMIO register access is now only used inside the
gpio_banks block, the gpio_read32 and gpio_write32 functions can be
moved to that block to reduce the visibility and enforce the usage of
the functions provided by the gpio_banks block.

The iomux_read8 and iomux_write8 functions can't be easily moved to the
gpio_banks block, since it's also used in the pre-SOC AMD chipsets that
use the ACPIMMIO access functions directly.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia0d6dea72c6bebbbe6ce545bedfc74f91e0042c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2021-09-08 00:15:30 +00:00
Felix Held
029a4a0b88 soc/amd/common/block/gpio_banks: factor out get_gpio_mux
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7d7a8c5a7188fd558a577352f8b246e61f3edd63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-08 00:15:09 +00:00
Felix Held
35cee38c71 soc/amd/common/block/i2c: move raw GPIO access functions to gpio_banks
The I2C code should use some GPIO API to access the GPIO registers
instead of accessing the GPIO MMIO regions itself.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I84dff381ad86e0c7f879f0f079186aec9cafc604
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-08 00:14:53 +00:00
Felix Held
96c4882d25 soc/amd/common/block/i2c: use common GPIO API in drive_scl
No need to do raw GPIO MMIO accesses when basically the same
functionality can be achieved by using existing APIs. Using the existing
GPIO API instead of raw GPIO MMIO register accesses allows containing
all direct GPIO MMIO accesses inside the common AMD GPIO code which will
be done in subsequent patches. Since the value parameter of gpio_set is
int, change the type of the val parameter of drive_scl to int as well
even though I'm not sure why a signed integer was used for this in the
common GPIO API. Since program_gpios already configures the SCL GPIOs as
outputs, gpio_set can be used in drive_scl which only sets the output
value, but doesn't configure the direction.

TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook
looks similar to the same as before during the reset_i2c_peripherals
call, but due to the additional overhead of the read-modify-write to the
GPIO register instead of just a write, the pulse width gets about 50%
longer. Since the udelay call in drive_scl still has an open TODO to
make this configurable and the pulses being longer is in the safe side,
this side-effect can be addressed in a follow-up patch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic323cebc1c83ecd6f0e1fbab419c69489d77face
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-08 00:14:35 +00:00
Felix Held
916cd50edc soc/amd/*/bootblock,early_fch: rework i2c_scl_pins configuration
drive_scl in soc/amd/common/block/i2c/i2c.c writes the raw GPIO MMIO
configuration register and drives it as output, so don't initially
configure the GPIO as input with no pull up/down. This is a preparation
to use the common AMD GPIO access functions instead of the raw register
accesses, since the gpio_set function only sets the output value, but
doesn't reconfigure the direction. Using gpio_output there instead would
reconfigure the direction as well, but would result in doubling the
number of MMIO accesses, so just configure the GPIOs correctly right
away to avoid that.

TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook
looks exactly the same as before during the reset_i2c_peripherals call.
This was probed at the SCL pad of the unpopulated I2C level shifter on
the side that is connected to the SoC.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8e94afe0c755a02abcc722d5094e220d8781f8f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56807
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08 00:14:17 +00:00
Felix Held
dfe253b497 soc/amd/picasso: select ADD_FSP_BINARIES if USE_AMD_BLOBS is selected
Since the FSP binaries for Picasso are present in the amd_blobs repo,
select the ADD_FSP_BINARIES option if the Kconfig option to check out
that repo is set.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9a8571730cf271ad5e113e5df87700882b3c5475
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-04 18:32:53 +00:00
Felix Held
4b027690b6 soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chips
southbridge/amd/pi/hudson uses the common GPIO bank access code from
soc/amd, but doesn't provide all functionality that would be needed to
use the full functionality. Add a Kconfig option that switches off some
functionality in the common SoC GPIO access code, so that more of the
functionality proviced by the common SoC GPIO code can be used in the
AMD binaryPI chipset and board code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib10d5d5580aab30a359aa001bb6fc7e9fdb8fc41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56783
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-03 15:51:37 +00:00
Angel Pons
28a16d960c src/*: Specify type of DIMM_SPD_SIZE once
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once.

Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-03 00:10:33 +00:00