This applies a configuration lock to the TPM IRQ pins for all brya
and brask variants.
BUG=b:208827718
TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests
GSC_PCH_INT_ODL is locked.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Icfc251152278c59f9a94b84fcd8c6d36c26bff62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This applies a configuration lock to the TPM I2C and IRQ GPIO for
all brya and brask variants.
BUG=b:208827718
TEST=cat /sys/kernel/debug/pinctrl/INTC1055\:00/pins suggests
I2C_TPM_SDL and I2C_TPM__SDA GPIO PINs are locked.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4f2a7014faeecd4701ea35ec77ef0e1692516b9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add platform_report_mode function which report current developer mode
status to the PSP. L1 widevine app in the PSP will use this information
to select key box.
BUG=b:211058864
TEST=build and boot guybrush
TEST=build picasso chrome os boards
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I04b5fcfa338b485b36f1b946203f32823385c0b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Followup will allow use of PARALLEL_MP with SMM_ASEG so
some guards need to be adjusted.
Change-Id: If032ce2be4749559db0d46ab5ae422afa7666785
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It was only evaluated on LEGACY_SMP_INIT path while model_106cx
has used PARALLEL_MP for a long time.
Change-Id: I90ce838f1041d55a7c77ca80e563e413ef3ff88d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Outside of the designware I2C driver the generic platform_i2c_transfer
function should be used instead, so don't make dw_i2c_transfer available
outside of this file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib8b6a08b6aa2cd63adc2ef69b828661fa0ed154a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Using enum cb_err as return type instead of int improves the readability
of the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic1812c4d8d2b4d9ad331a787bd302a4f0707c1fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Using enum cb_err as return type instead of int improves the readability
of the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I55e6d93ca141b687871ceaa763bbbbe966c4b4a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Using enum cb_err as return type instead of int improves the readability
of the code. This commit only changes the return value of the static
functions in this file keeping the external interface identical.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I80300e0b24591fc660c3134139b9257e002cdbbb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
size_t is defined in stddef.h and not stdint.h, so include types.h to
get both.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3782d3a949b72d1530ebd8078c46bc695f76dc4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This will provide the definitions for size_t, uint32_t and uintptr_t.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icda8d458565bf981545d720d612cbdace04bedd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This is to reduce difference with linux v5.16.
Change-Id: I7abd4d8eed856eee841422515db2ff7f50ecd0a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
New platforms have additional Primary to Sideband bridge besides the PCH
P2SB. This change puts the common functions into the P2SB library.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I63f58584e8c3bfe42cdd81912e1e5140337c2d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use PAD config macro to add lock support for all the gpios used
in CB:58352 CB:58353.
BUG=b:211573253
TEST=Boot to OS, issue warm reboot and see no issue with any IP
enumeration
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I558bab39f935ab31a89541c6498a73af70cbf9ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Aggressive Link Power Management are no longer supported on these
mainboards and must therefore be disabled. This feature can have a
negative impact on the real-time behavior of the systems.
TEST:
- Boot into system software on mc_apl1
Change-Id: I8b08381743018790a20273ea1f61e5b0a56e6015
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add a devicetree option to disable SATA Aggressive Link Power
Management. ALPM is a method of saving power. The corresponding FSP-S
UPD parameter is enabled by default. It may be that this feature is
unwanted, for example for a real-time system. Therefore, allow to
disable ALPM using the devicetree.
Change-Id: Ica8920a87ebebe83f5d8cb4d6c8c0a6105e183e4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. Samsung K4U6E3S4AA-MGCR
BUG=b:214460184
TEST=emerge-dedede coreboot
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ief75fcb7a8f1c25feaf05b1535a9528a351b23b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Galtic has a rare stability issue.
The symptom is display black screen while switching to secure mode,
normally it will occurred at the last step of factory side
and it'll follow by some specific SOCs.
Slowing the initial core display clock frequency down to 172.8 MHz
as per Intel recommend for short term solution for Gal series.
The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0
(172.8 MHz) for Galtic.
BUG=b:206557434
BRANCH=dedede
TEST=Build firmware and verify on fail DUTs.
Check the DUTs can boot up in secure mode well.
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ic059ab306f80a6d01f4b0a380a3b767d3245478d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61103
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PCR_PSF3_TO_SHDW_PMC_REG_BASE for Alderlake-N.This value is updated
from the FSP code.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61148
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Alder Lake N has eMMC storage device. Select SOC_INTEL_COMMON_BLOCK_SCS
Kconfig for Alder Lake N.
Change-Id: I577ffdc80ef09471309c827551a347d4397a33d1
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Alder Lake N has eMMC storage device. Add PCR Port ID for it.
Reference: Alder Lake N platform EDS Doc# 645548.
Change-Id: I6dc494d1748e66b8b4058954f127ec226863e8af
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Add definitions for GPP_I GPIO group pins on Alder Lake N SOC and GPIO
IRQ routing information.
GPP_I GPIO group belongs to GPIO community 1. Hence GPIO community 1 in
Alder Lake N contains GPP_S, GPP_I, GPP_H, GPP_D GPIO groups.
GPIO groups 1-6 in Doc# 645550 Chapter 36 corresponds to GPIO
communities 5-0 respectively.
BUG=b:213535859
Change-Id: Ia71a399c03cb7d098a381bd9439d448e8a620761
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61106
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is to reduce difference with linux v5.16.
Change-Id: I3bdf880c8b6068467665865b7cf1249d1047e833
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This is to reduce difference with linux v5.16.
Change-Id: I1b7bc2b4ec832f0abeda215c381856a5ec153883
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This is to reduce difference with linux v5.16.
Change-Id: I4aa7abce83b41ccd5129717cd3bf85be19ec4807
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Also use '$minimum_perl_version'.
This is to reduce difference with linux v5.16.
Change-Id: I7c2f5d5c9853dc8ddc8f89a5e2edd6c8613ba790
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This is to reduce difference with linux v5.16.
Change-Id: Ifeb9c4406737fa24f9bd803af48d8b8d17654940
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
ADL has 4 TBT root ports which are PCIe compliant. TBT uses PCIe
coalescing logic where in case root port 0 is disabled, other enabled
root port is remapped to port 0.
coreboot handles this remapping scenarios for PCH and CPU PCIe root
ports and not for TBT root ports.
This patch uses the same function used for PCIe remapping to update
devicetree based on coalescing and SoC needs to pass correct function
number and number of slots.
BUG=b:210933428
BRANCH=None
TEST=Check if TBT remapping happens correctly and ACPI tables are
generated correctly.
Change-Id: Ied16191d6af41f8e2b31baee80cb475e7d557010
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
pcie_rp_update_devicetree function takes pcie_rp_group strcuture
as an argument and SoC code passes the parameter in this structure.
This pointer can be NULL and common code may try to dereference
this NULL pointer.
Also, group might have no data and SoC may pass this by indicating
group count as zero (For example, for CPU or TBT root ports).
These checks will prevent function from executing redundant code
and returning early from the call as it's not required.
BUG=b:210933428
BRANCH=None
TEST=check if function returns early for group count 0 and there is
no issue while booting board in case group count = 0.
Change-Id: I132319bb05fdef1590c18302fc64cc76e15bea6d
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Create the crota variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:215443524
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_CROTA
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ic8f1a0bde286d5d014dfdf87c2a417ca6ff8b3a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Subrata Banik