Most of the X11 boards with socket LGA1151 are basically the same boards
with just some minor differences like different NICs (1 GbE, 10 GbE),
number of NICs / PCIe ports etc.
There are about 20 boards that can be added, if there is a community for
testing.
To be able to add more x11 boards easily like x11ssm (see CB:35427) this
restructures the x11ssh tree to represent a "X11 LGA1151 series". There
were multiple suggestions for the structure like grouping by series
(x10, x11, x...), grouping by chipset or by cpu family.
It turned out that there are some "X11 series" boards that are
completely different. Grouping by chipset or cpu family suffers from the
same problem. This is why finally we agreed on grouping by series and
socket ("X11 LGA1151 series").
The structure uses the common baseboard scheme, while there is no "real"
baseboard we know of. By checking images, comparing logs etc. we came to
the conclusion that Supermicro does have some base layout which is only
modified a bit for the different boards.
X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we
expect the other boards to have mostly the same device tree, there is a
common devicetree that gets overridden by each variant's overridetree.
Besides that some very minor modifications happened (formatting, fixing
comments, ...) but not much.
Documentation is reworked in CB:35547
Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modify IRQ pin from D21 to A21 and support wake-up from touchpad
BUG=b:141519690
TEST=build bios and verify elan touchpad works fine
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6cc5b780ffcee24f1f2a04e88c30628ceb5904e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35551
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
new DDR particle:
1. Samung K4A8G165WC-BCWE
2. Hynix H5AN8G6NCJR-XNC
BUG=b:139085024
BRANCH=master
TEST=rework new source to DUT and re-flash bios to DUT and
verify DUT will bring up successfully
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I0d039af53938086733308a081a77a7398e7bf5d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
It is only called in ramstage. Even if it was called in
romstage, execution flow is such that BSP and AP CPUs
should not be able to enter update_microcode() routine
concurrently.
Also the Kconfig guarding the spin_lock() calls are not
selected nor are the lock variables declared for these
platforms.
Change-Id: I1c2e106f10e8420e942b3ed082c677c0db95557c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35586
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The script had a couple of bugs:
* It didn't create the required directory under variants/
* It was treating the wildcard as literal and so couldn't
find variant files to copy.
V.2: Drop verbose cp && fixup wild card usage.
Change-Id: Ie6f4179014b79ea45d0fcf406ca192046438dbf7
Signed-off-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
CB:29633 switched platform to use sb/common spi implementation,
which worked until CAR_GLOBAL was removed in CB:30506.
Revert the changes back to usage of CAR_GLOBAL in the common spi
driver so that flashconsole will work again in romsatge for
fsp_broadwell_de.
Test: verify flashconsole functional on out-of-tree Broadwell-DE board
Change-Id: I72e5db1583199b5ca4b6ec54661282544d326f0f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add the configuration 'Juniper' for the new mainboard.
BUG=b:137517228
TEST=make menuconfig; select 'juniper' and build
Change-Id: I94e3ac7f6de3fecf177e344cb217eaecf6362d69
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Now that SOC_INTEL_COMETLAKE is selected by default in Kconfig,
utility to create a new variant does not need to do that anymore in
Kconfig.name
Change-Id: If68bcf14e2e0812d4f4dcb99371c65790154ff62
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
All variants of hatch are using Comet Lake and so the selection can be
done in Kconfig without requiring each variant to do the same.
Change-Id: Ief34296334ede5ba0f5f13381e92427ccc440707
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Eltan is missing in the vendor index.
Documentation of the eltan vendorcode is availlabe already.
Add eltan to vendor index.
BUG=N/A
TEST=N/A
Change-Id: I51fe64da91499f0ea7bf97fc240f4e263470c146
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Sort the names of all variant mainboards in an ascending order.
Change-Id: I19d502298744c0e0cbc91eb836c62ca90cdb9a5c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Enable VBOOT in Kconfig and provide a flashmap that includes all the
needed sections for VBOOT support.
Change-Id: I3d58094256d2730dbd249291a8f1ed8df9dfe62d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The implementation of udelay() with LAPIC timers
existed first, as we did not have calculations
implemented for TSC frequency.
Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We can use intel/common implementation for tsc_freq_mhz().
Change-Id: I728732896ad61465fcf0f5b25a6bafd23bca235e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34199
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix regression from commit ecea916
cpu/intel/common: Extend FSB detection to cover TSC
MSR_EBC_FREQUENCY_ID (0x2c) was not defined for affected
CPU models and rdmsr() caused reset loops. Implementations
deviate from public documentation.
Change to IA32_PERF_STATUS (0x198) already used in i945/udelay.c
to detect FSB to TSC multiplier.
Change-Id: I7a91da221920a7e7bfccb98d76115b5c89e3b52e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
To be reproducible, TZ LANG LC_ALL should be set early
in the build process to be always used.
Change-Id: Iad802968347c8d41f974af930e0d0ad5b66719cb
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This was causing a failure when building platforms with no bootblock
when building with make -jXX
Change-Id: Ic4cd4fe8ac82bd1e9ce114dbd53763538d125af3
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The Razer Blade Stealth H2U is a KabyLake System using:
- Intel KBL 7500U
- ITE8528E SuperIO
- Intel 600P Series NVMe SSD
- Either four MT52L1G32D4PG (16GB) or MT52L512MB32D4PG (8GB)
of soldered memory in dualchannel mode
- (Optional) Touchscreen
- HDMI 2.0a via DP-1: Paradetech PS175
- AlpineRidge Thunderbolt 3 controller
- TPS65982 USB-PD power switch / multiplexer
Even though it has a 16MB chip equipped (W25Q128.V) only the first 8MB
are used and mapped via IFD. The rest is left empty (0xFF). The flash is
not secured in any way and can be read via flashrom. It should be the
source for this port's IFD and ME blobs.
Working:
- USB-A Ports left and right
- Speakers
- Touchscreen (USB)
- Onboard Keyboard in Linux
- NVMe SSD
- SeaBIOS, Tianocore and Grub Payloads
- Webcam
- Powersaving Modes
- Battery state and LID switch, sometimes slow to update.
- Touchpad (I2C-HID)
- Headphones
Not part of this commit:
- Thunderbolt / USB-C (Requires advanced EC signaling)
- Full HDMI support (Currently requires plugged connection at boot)
Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
CONFIG_MAINBOARD_DEPTHCHARGE is used to override the Board
config for depthcharge which inherit from CONFIG_MAINBOARD_PART_NUMBER.
This is mainly to avoid depthcharge config duplication.
Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Change-Id: I6cbc93ca38ad6deeca2c2fb7770024a24233b6f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
When accessing register with multiple bit fields, the common approach is
to use clrsetbits_le32, for example:
clrsetbits(®, (1 << 0) | (0x3 << 1) | (0x7 << 10),
(1 << 0) | (0x1 << 1) | (0x5 << 10));
This hard to maintain because we have to calculate the mask values
manually, make sure the duplicated shift (offset) was set correctly.
And it may be even worse if the value to set will be based on some
runtime values (that many developers will do a if-block with two very
similar argument list), and leaving lots of magic numbers.
We want to encourage developers always giving field names, and have a
better way of setting fields. The proposed utility macros are:
DEFINE_BITFIELD(name, high_bit, low_bit)
EXTRACT_BITFIELD(value, name)
WRITE32_BITFIELDS(addr, name, value, [name2, value2, ...])
READ32_BITFIELD(addr, name)
Where a developer can easily convert from data sheet like
BITS NAME
26:24 SEC_VIO
Into a declaration
DEFINE_BITFIELD(SEC_VIO, 26, 24)
Then, a simple call can set the field as:
WRITE32_BITFIELDS(®, SEC_VIO, 2);
That is much easier to understand than
clrsetbits_le32(®, 0x7 << 24, 0x2 << 24);
And to extract the value:
READ32_BITFIELD(®, SEC_VIO)
That is equivalent to:
(read32(®) & 0x3) >> 24
Change-Id: I8a1b17142f7a7dc6c441b0b1ee67d60d73ec8cc8
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35463
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable root port IOU0 to which built-in NIC is attached.
TEST=on OCP monolake, hide built-in NIC and make sure OS does not report
built-in NIC
Change-Id: I2384e7dd073355f0ced2902ac2d8418996b1c5aa
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Add function to hide IIO PCIe root ports.
TEST=On OCP Monolake, hide built-in NIC PCIe root port [0.2.2 and 0.2.3]
and make sure OS does not detect built-in NIC.
Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
- configure DMA fw_cfg
- add support to read using fw_cfg_dma
- provide fw config version id info in logs
BUG=N/A
TEST=Build and boot using qemu-i440fx.
Change-Id: I0be5355b124af40aba62c0840790d46ed0fe80a2
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbps)
while those with discrete DRAM can only run at 3200Mbps. This patch
enables 3600Mbps for eMCP DDR for better system performance.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly and stress test passes on Kukui
Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Fill the dimm info struct to make SMBIOS type 17 appear.
TESTED=Up Squared
Change-Id: I4de63362c8fea8a886594cdcf0eec48421afb605
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34564
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For platform independend exposure of FMAP through a kernel module
cache the FMAP in CBMEM. In addition add a pointer in coreboot tables
pointing to the introduced CBMEM area.
To not waste the allocated DRAM, use the cached CBMEM in RAM enabled
stages if possible.
Tested on qemu using
https://github.com/9elements/linux/commits/google_firmware_fmap2
Tested on QEMU and Supermicro X11SSH-TF.
Change-Id: I4e01c573c3edfa34dbba5fe7604d4f6e18b584d5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Drop unused CNF2_LPC_EN, as there is no device which uses IO 0x4e/4f.
Do not use the mainboard model to set COMA_LPC_EN. Make use of
NO_UART_ON_SUPERIO instead, as it is more future-proof.
Change-Id: Iac49250b0f509a42012f82db8aa85ba85559c66f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
BUG=b:140545732
TEST=build bios and spd index set to 6, verify DUT bring up normally
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I337b0bdcd37a9c4baacccbc6786968031a41b31e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35511
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Read-modify-write needs to access the same register. Numerically
both used defines are 0x3e, while register implementations are
not identical but only similar.
Change-Id: I9348b855320f86868e2d3ef76d3b8d7a4ab7fae0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
CdClock does not need to be set because the board does not use IGD.
Change-Id: I6835ccdf80530f9efc6fdeb0363dcf9267f99d21
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Implement Locator and Bank fields (as reported by dmidecode) to match
vendor BIOS.
TEST=on OCP monolake, run dmidecode tool and see that "Locator" field
matches expectation.
Change-Id: Ia271ff1e596ba469cf42e23d8390401c27670a27
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Currently "DIMM numbers" increase monotonically for all the channels. However,
commonly DIMMS are numerated on per-channel basis. This change makes numeration
match the convention.
TEST=on OCP monolake, run dmidecode tool and see that "Locator" field matches
expectation.
Change-Id: I3e7858545471867a0210e1b9ef646529b8e2a31c
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35318
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the new SPI code from common folder, delete spi.c. SPI related macros
must be single defined, in southbridge.h if they are used by files other
than the common SPI code, fch_spi.h if they are only used by the common
SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h,
because it can change between SOC.
BUG=b:136595978
TEST=None, code already tested with grunt.
Change-Id: I68008ce076d348adbdabf7b49cec8783dd7134b4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Use the new SPI code from common folder, delete spi.c. SPI related macros
must be single defined, in southbridge.h if they are used by files other
than the common SPI code, fch_spi.h if they are only used by the common
SPI code. The only exception is SPI_FIFO_DEPTH which must be in southbridge.h,
because it can change between SOC.
BUG=b:136595978
TEST=Build and boot grunt using new SPI code, with debug enabled. Check
output.
Change-Id: I639973d993316a10daa7564462e689b2c183f536
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Andrey Petrov