Commit Graph

17149 Commits

Author SHA1 Message Date
Martin Roth 3f1abb84e8 SeaBIOS: Update SeaBIOS from repo when using master branch
Previously the SeaBIOS directory would never get updated after the
initial clone because the tag would always match. This can be shown
by noticing that the text 'Fetching new commits from the SeaBIOS
git repo' is never seen.

This change will always try to pull the latest code if 'Master'
is selected.

Change-Id: I460e2fb0c6f683a0f85343d164880c2d9e6d95cc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13947
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-11 17:56:05 +01:00
Martin Roth 1484c03916 crossgcc/buildgcc: Add comment about URLs and jenkins builder
Add a comment to try to lower possible confusion later if the jenkins
tool builder fails to build a new tool.  The URLs for the packages that
are downloaded are checked against known locations so that someone can't
maliciously download a package from somewhere and run it on the build
server.  This provides a little bit of security, but could confuse
someone if they don't realize it.

Change-Id: I7858e3d86fc705b480f6792b6adf3d5349580e01
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13955
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-11 17:55:38 +01:00
Martin Roth 2114880f66 crossgcc/Makefile.inc: Add target for jenkins toolchain test build
We've recently added a jenkins test builder for the coreboot toolchain.
This patch allows what it builds to be controlled from the makefiles
checked into git instead of by a rule on the builder itself.

Change-Id: I65f70bac5ab97ecb27aae93ee370b26a2ab1f9c0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13954
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-11 17:01:11 +01:00
Timothy Pearson 2e1f73181a nb/amd/mct_ddr3: Require minumum training quality for both read and write
The existing MCT code proceeded to the next DRAM training phase if
the minimum lane quality standard passed for either the read or
write direction.  Ensure that both pass for a given set of delay
values before proceeding to the next training phase.

Change-Id: I2316ca639f58a23cf64bea56290e9422e02edf1c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13993
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11 16:58:55 +01:00
Timothy Pearson 50583f0e1f nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latency
The AMD Family 15h BKDG rev. 3.14 indicates that the maximum read latency
must be calculated prior to DQS position training, however the read
latency calculations use read DQS delay values that have not been
set prior to DQS position training.

Set the read DQS delay values to 1UI (i.e worst case) before calculating
the read latency prior to DQS position training.

Change-Id: I6ae88c891e92b21dc0ca3c47b8f3d269f83b3204
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13995
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11 16:57:49 +01:00
Timothy Pearson 8eb221deaf nb/amd/mct_ddr3: Properly initialize arrays and add bounds checks
A couple of arrays were not properly initialized.  This
did not appear to affect operation of the codebase however
it led to some ugly values being displayed when debugging
was turned on.

Also bounds check an array index; as before this did not
appear to affect operation but was a potential point of
failure.

Change-Id: I243b7197a74aed78ddca808eb3b0f35f1fe9d95a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13934
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11 16:56:56 +01:00
Timothy Pearson bbfcf62512 nb/amd/mct_ddr3: Restore previous DQS delay values on failed loop
Change-Id: Iacfcd7f379d09a633973b4c3ef3cbb97e6d1f09f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13931
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11 16:56:17 +01:00
Andrey Petrov 7109304cf2 soc/intel/apollolake: Avoid hardcoding CAR region size for FSPM
Instead of having to supply CAR memory region during compilation
time it is possible to determine it in runtime. FSP2.0 blobs carry
a copy of UPD structure pre-populated with 'default' values. The
default value for StackSize is actually the real value blob needs.

Change-Id: I298e07bb12470ce659f63846ab096189138e594f
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14001
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-11 16:55:51 +01:00
Paul Menzel 468dc33325 payloads/seabios: Update version number in Kconfig
Fix up commit 4f66648c (payloads/seabios: Upgrade stable from 1.9.0 to
1.9.1), forgetting to update the version number displayed in the Kconfig
menu, by updating the string to 1.9.1.

Change-Id: Idb395d0ea65bcf91c7c9645fd76d428936e91587
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/14010
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
2016-03-11 16:54:23 +01:00
Iru Cai 3677520fd9 arch/x86/smbios: fix length calculation for SMBIOS type 17
Different DIMM modules give different SMBIOS type 17 lengths, so we
can't use `meminfo->dimm_cnt*len' for entry struct size, otherwise
it'll give a wrong SMBIOS size when two or more different DIMMs are
installed on the machine.

Change-Id: I0e33853f6aa4b30da547eb433839a397d451a8cf
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/14008
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-03-11 16:53:39 +01:00
Martin Roth f2e0461d89 Kconfig: remove COMPRESS_PRERAM_STAGES option from x86
Instead of just defaulting to disabled, remove the option for
x86 since it doesn't work there.

Change-Id: I2b84b9f866f9231943e573b873c970f420c7c9a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/14017
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2016-03-11 16:52:38 +01:00
Andrey Petrov 447d9489a2 cbmem: Fix cbmem_add_bootmem()
Change 13363 (555d6c2) introduced a bug where cbmem_add_bootmem() was
converted to use a new function. Unfortunately instead of passing a
pointer, NULL was passed due to type confusion. This change fixes that
problem by passing address of stack variable instead of NULL.

Change-Id: Ib8e1add3547cda01f71bf1dea14d3e58bdd99730
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/14033
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-03-11 09:52:46 +01:00
Alexander Couzens c7a1a3e994 northbridge/i945/gma: Re-enable NVRAM tft_brightness
Commit 71512b2c (northbridge/i945/gma: fix build error with native graphics init)
unintentionally changed the code to ignore the NVRAM setting
`tft_brightness`. Revert that hunk to restore the original behavior.

Change-Id: Iffdfc5272732bad3476f35ddac1f5a7564270531
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/14002
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-11 00:48:54 +01:00
Andrey Petrov a2176d8ef6 soc/apollolake: Add memory and reserve MMIO resources
This adds most important MMIO reserved memory resources,
real DRAM memory resources, and some DRAM resources that
can not be used as RAM for whatever reason.

Change-Id: Id5a80cf18d67ace991e8046fa46c4b7ed47c626a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13360
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-10 23:11:10 +01:00
Alexandru Gagniuc 555d6c2161 cbmem: Add utility to get memory region occupied by cbmem
Change-Id: I8e57c23565f173afc0f4d450579b8bfb35aeb964
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13363
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-10 23:08:26 +01:00
Andrey Petrov 1e70cda320 soc/intel/apollolake: Avoid UART BAR relocation at ramstage
UART bar gets overwritten during resource allocation stage. As result
the serial driver ends up using stale BAR so serial output does not
work. This driver simply tells resource allocator not to change BAR
of UART device.

Change-Id: I81f4f04089106c80bea97f0bbaba890df00c8ac5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13997
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-03-10 23:02:57 +01:00
Andrey Petrov e953dce7c4 soc/intel/apollolake: Add ids of internal SoC PCI devices
Change-Id: I6a632ca7d4a19c4973c41bb102f97e0836f27a5e
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13996
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-03-10 23:02:39 +01:00
Lance Zhao ffc51d475a mainboard/intel/apollolake_rvp: Populate static devicetree
Add configuration in accordance to "PCI Configuration Matrix".

Change-Id: If1f60486d802a6595aed03d95e0d20fc7db21bd2
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13926
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-03-10 23:02:10 +01:00
Andrey Petrov 70efecd4a2 soc/intel/apollolake: Add chip initialization
Change-Id: I54532b71c7649f7eeccbb2213b31418cfdbfb00c
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13911
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-10 23:01:31 +01:00
Ravi Sarawadi 9d903a1dd3 soc/apollolake: Enable all CPU cores using the parallel MP lib
This is the minimal setup needed to get all CPU cores enabled. That
includes sending an IPI to APs and setting up MTRRs. Microcode updates
are not performed for two reasons:
* CSE (Converged Security Engine) upgrades the microcode before
  releasing reset
* Microcode update files are not available at this point in time

Change-Id: Ia1115983696b0906fb4cefcbe1bbe4fc100751ca
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-03-10 22:57:00 +01:00
Martin Roth 7760261db7 src/lib/trace.c: Make address size generic
On platforms that didn't use 32-bit addresses, enabling the
CONFIG_TRACE option (Trace function calls) would break the build due
to a cast from a pointer of a different size.

This fixes this warning:
src/lib/trace.c:29:58: error: cast from pointer to integer of different
size [-Werror=pointer-to-int-cast]

Change-Id: Iaab13c1891b6af7559ea6982ecc6e74c09dd0395
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13962
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-10 17:28:26 +01:00
Stefan Reinauer 7e3903b1f1 cpu/via/c7: Don't manually include udelay_io.c
Use UDELAY_IO selected by CPU_VIA_C7, so no manual inclusion
(or secondary UDELAY implementation) is needed

Change-Id: Ib086a1bfe8ffca5757bf553c5a62a45da7a410b6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13782
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-10 16:56:23 +01:00
Stefan Reinauer 3d840d09ae northbridge/intel/i440bx: Unify UDELAY selection
Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i440BX boards in the chipset.

Change-Id: I411191927f3fba1d0749edcf79378e8013fb195a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13781
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-10 16:55:35 +01:00
Georg Wicherski 422bf6b472 mainboards/google/auron_paine: add new port
Add a port of Auron_Paine based on upstream Auron and the Auron_Paine
code originally from commit bd61dfd in Google branch
firmware-paine-6301.58.B .

Change-Id: I3a1faec3195a81bb3a6496b8bd610fc8a89e66aa
Signed-off-by: Georg Wicherski <gwicherski@gmail.com>
Reviewed-on: https://review.coreboot.org/11907
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-10 16:54:39 +01:00
Lance Zhao 1eb1e3b8bf mainboard/intel/apollolake_rvp: Add memory training config
Pass memory training information to MemoryInit, so memory
training can be completed.

Change-Id: Icb1bf308b77a1c8481313c259c3f3dd1d8379863
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13870
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-09 17:52:06 +01:00
Julius Werner fffee873c8 Makefile: Add build-time overlap check for programs loaded after coreboot
On non-x86 platforms, coreboot uses the memlayout.ld mechanism to
statically allocate the different memory regions it needs and guarantees
at build time that there are no dangerous overlaps between them. At the
end of its (ramstage) execution, however, it usually loads a payload
(and possibly other platform-specific components) that is not integrated
into the coreboot build system and therefore cannot provide the same
overlap guarantees through memlayout.ld. This creates a dangerous memory
hazard where a new component could be loaded over memory areas that are
still in use by the code-loading ramstage and lead to arbitrary memory
corruption bugs.

This patch fills this gap in our build-time correctness guarantees by
adding the necessary checks as a new intermediate Makefile target on
route to assembling the final image. It will parse the memory footprint
information of the payload (and other platform-specific post-ramstage
components) from CBFS and compare it to a list of memory areas known to
be still in use during late ramstage, generating a build failure in case
of a possible hazard.

BUG=chrome-os-partner:48008
TEST=Built Oak while moving critical regions in the way of BL31 or the
payload, observing the desired build-time errors. Built Nyan, Jerry and
Falco without issues for good measure.

Change-Id: I3ebd2c1caa4df959421265e26f9cab2c54909b68
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13949
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-09 17:07:14 +01:00
Stefan Reinauer 0819a47d14 northbridge/intel/gm45: Use TSC for ramstage timer per default
This is a step towards isolating the timer drivers.

Change-Id: I4c9349054be0cf520cd4407be9fb393b664223a4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13922
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-09 17:04:21 +01:00
Martin Roth 5ad9acaba6 payloads: Move secondary payloads inside of a submenu
To keep the list of 'secondary' payloads from cluttering the payloads
menu, move them into their own menu under the payloads menu.  Then they
don't need any dependencies other than the architecture.

Change-Id: I95119750c6ef627ef0de9b5f5cbad085a51ac2bb
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13941
Tested-by: build bot (Jenkins)
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-09 17:03:21 +01:00
Martin Roth 679755778b Makefile: Update payload clean targets
Move payload clean targets into payloads/Makefile.inc
Add clean targets for coreinfo, nvramcui, Memtest86+

Change-Id: I70c13582311dfba3e309805053159f8a039cb109
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13940
Tested-by: build bot (Jenkins)
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-09 17:01:56 +01:00
Aaron Durbin 0fcd6f912b drivers/intel/fsp2_0: remove struct resource usage
There's no need to use a struct resource type for
fsp_find_reserved_memory(). struct resource is mainly associated
with a device and that memory is added to cbmem after memory init.
Other uses ins FSP 2.0 just use struct range_entry. Use that
instead for consistency.

Change-Id: Id7d39da1c2e23f97cdaafd7f5d281cefa6fee543
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13960
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09 16:47:40 +01:00
Aaron Durbin 9b28f0023c drivers/intel/fsp2_0: add TODOs to fix deficiencies
The FSP 2.0 implementation doesn't handle FSP modules for
SoCs that are required to be XIP. There is no notion of
"loading" in that situation where one should be copying
anything anywhere.

Additionally, the loading code does not handle overlaps within
the current running program which is doing the loading.

Change-Id: Ide145581f1dd84efb73a28ae51b3313183fa127a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13959
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09 16:47:11 +01:00
Aaron Durbin 40672becaa drivers/intel/fsp2_0: don't leak resources
rdev_mmap() was not followed by rdev_munmap(), thus leaking
resources. Fix the leak.

Change-Id: Ibdd30d6b64616038013b4bb748f2ad4a98db5472
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13958
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09 16:46:52 +01:00
Aaron Durbin ac1c9ece23 soc/intel/apollolake: correct comment to reference top of CAR
The memory provided to MemoryInit() for its own usage is at the
top of the CAR region.

Change-Id: I8685b5ab138182e24123b14cac6f7b32e5e784d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13957
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09 16:46:32 +01:00
Aaron Durbin e884592209 lib/memrange: add function to initialize range_entry
In order to enforce the semantics of struct range_entry provide
an init function, range_entry_init(), which performs the field
initialization to adhere to the internal struture's assumptions.

Change-Id: I24b9296e5bcf4775974c9a8d6326717608190215
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13956
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-09 16:46:16 +01:00
Nico Huber 566dd35768 Add option for "timeless" builds
Builds with BUILD_TIMELESS=1 shall always give a bit identical output
for stable inputs. This should help verifying that resulting rom files
stay the same across commits that shouldn't change the outcome.

To be useful for builds that rely on 3rdparty/arm-trusted-firmware,
this needs a similar change there.

Change-Id: Ia0a22e3e79fbd0abbd2a9071ecbeef6541787a08
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13412
Tested-by: build bot (Jenkins)
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-03-09 15:25:05 +01:00
Paul Menzel 4f66648c09 payloads/seabios: Upgrade stable from 1.9.0 to 1.9.1
SeaBIOS 1.9.1 was released on February 15th, 2016 [1][2] with the changes
below.

```
$ git log --oneline --reverse rel-1.9.0..rel-1.9.1
3403ac4 build: fix typo in buildversion.py
fe4154e xhci: Check for device disconnects during USB2 reset polling
c016236 xhci: Wait for port enable even for USB3 devices
0240428 sdcard: Only enable error_irq_enable for bits defined in SDHCI v1 spec
fe8d986 sdcard: fix typo causing 32bit write to 16bit block_size field
e902d3f nmi: Don't try to switch onto extra stack in NMI handler
dc6498e scsi: Do not call printf() from scsi_is_ready()
6027043 coreboot: Check for unaligned cbfs header
73f00bc fw/pci: do not automatically allocate IO region for PCIe bridges
b3ef39f biostables: Support SMBIOS 2.6+ UUID format
```

[1] http://www.seabios.org/Releases#SeaBIOS_1.9.1
[2] http://seabios.org/pipermail/seabios/2016-February/010493.html

Change-Id: I4bc8224c2a80cbcce54621e941a9c3a92ca04215
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/13933
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-03-09 15:22:56 +01:00
Aaron Durbin 2a08137fee x86 chipsets: utilize x86_setup_mtrrs_with_detect()
For all the chipsets which were performing the following sequence:
  x86_setup_fixed_mtrrs();
  x86_setup_var_mtrrs(cpuid_eax(0x80000008) & 0xff, 2);

Replace that with x86_setup_mtrrs_with_detect() since it is equivalent.

Change-Id: I9f362dbf38942d675f615d22b9e5770ce65e5a08
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13936
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-03-08 23:58:01 +01:00
Julius Werner f545208597 nyan: Fix timestamps and CBFS SPI integration
Nyan is an old board that was committed before several core code
modernizations to timestamp and CBFS code. Not all of those later
patches were correctly integrated with old boards like this, and the
core code has evolved to a point where it doesn't actually boot anymore.

This patch fixes that issue and brings the Nyan boards more in line with
how later ARM platforms look.

BRANCH=None
BUG=None
TEST=My Blaze boots again.

Change-Id: I3277a2f59ad8ed47063f7f6b556685313b1446f8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6a1679e342a7adc2b2371b6e3f69a898a7a5c717
Original-Change-Id: I2a0a2abbd79b4b5f756125dcbb6cbd9441016d4e
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/328543
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/13832
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-03-08 22:04:22 +01:00
Duncan Laurie 61980af95d mainboard/skylake: Include WRDD method in WIFI ACPI device
Include the code to add the WRDD method to the existing
WiFi Device in the mainboard ACPI code.

BUG=chrome-os-partner:50516
BRANCH=glados
TEST=boot on chell with 'region'='us' in VPD and see that it is
properly read out by calling WRDD method on the WiFi device.
Compile for the other platforms that are modified.

Change-Id: Ibcff7585744071ba9018d0ba50e274e63365b150
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b74bb553415f7ce224ddcb0c2c5ae509b8fed516
Original-Change-Id: Ieb24e0e64974ee3686d14a234e148f5d07fc8b12
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329296
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13840
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08 21:44:42 +01:00
Duncan Laurie 3d3b76b832 skylake: Add and fill out CID1 NVS field
Add a country identifier field to NVS and populate it with the
call to wifi_regulatory_domain() which will (by default) do a
lookup for the 'region' identifier in VPD on a Chrome OS device.

BUG=chrome-os-partner:50516
BRANCH=glados
TEST=build and boot on chell

Change-Id: Ie7531848e620095732772c22156a85b7f8a6df5c
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: dafdb3760a0302e3effdc0e83977c1bfd5c9d3b2
Original-Change-Id: Ic83ab008045a469d0e0756f7e4d42f1b3894c529
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329295
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13839
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-08 18:43:11 +01:00
Duncan Laurie 8951ed8b90 intel/wifi: Add WRDD ACPI method
Add an ACPI file containing a generic WRDD method that is used
by Intel wireless kernel drivers to determine the country code
to be used for regulatory domain configuration of the wireless
radios.

This requires an NVS variable called 'CID1' to provide an
ISO-3166-2 alpha-2 country code or it will just return 0 instead.

This is implemented as a bare method because this needs to be
included directly into the wifi device that is defined by the
mainboard as it may have board-specific settings like _PRW that
need to be provided as well.

BUG=chrome-os-partner:50516
BRANCH=glados
TEST=boot on chell with 'region'='us' in VPD and see that it is
properly read out by calling WRDD method on the WiFi device.

Change-Id: I27a5e27f65d05ff62a0e79a87a32c1ef0c5d0ef3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 2da0cf76ca3cc5e3dfbc4a0859733523de780cf5
Original-Change-Id: I9d83c3938cceafc77ef8747a5c47f586ee84437e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329294
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13838
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-08 18:42:32 +01:00
Huang, Huki 339886cff4 Chromeos: Modify wifi_regulatory_domain to use "region" key in VPD
In ChromeOS VPD spec the right name is "region".

Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/322851
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: mukesh agrawal <quiche@chromium.org>
(cherry picked from commit 21ea0663e7f3ffe3aaea6b6ce0e1216fcd9ca23e)

BUG=chrome-os-partner:50516
BRANCH=glados
TEST=build and boot on chell

Change-Id: I4ba9a9c65af3732fa263030640495ab5bea91d1f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 848f18e731eb11dd3037d12607d7364f95e64e34
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Ib96036f9cd76449f170af5c3dd6ef6e8e91ded94
Original-Reviewed-on: https://chromium-review.googlesource.com/329293
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13837
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-08 18:41:57 +01:00
Felix Durairaj 7f761658a5 lib: Implement framework for retrieving WiFi regulatory domain
Platforms that need to initialize WRDD package with the regulatory domain
information should implement function wifi_regulatory_domain.
A weak implementation is provided here.

Signed-off-by: fdurairx <felixx.durairaj@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/314384
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Tested-by: Hannah Williams <hannah.williams@intel.com>
(cherry picked from commit c25d7221679d1fab830d614eeabfa3436bce6ac1)

BUG=chrome-os-partner:50516
BRANCH=glados
TEST=build and boot on chell

Change-Id: I1cbdf4e940b009c74ee8ed8f4fca85f4f5c943b2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 27bba336e620a2d3d331e350d4f46164e337fabc
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: I84e2acd748856437b40bbf997bf23f158c711712
Original-Reviewed-on: https://chromium-review.googlesource.com/329291
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-08 18:41:33 +01:00
Lee Leahy d76d60bf56 soc/intel/quark: Set the UPD values for MemoryInit
Set the UPD values for MemoryInit.
*  Update the FspUpdVpd.h file which specifies the parameters for
   MemoryInit.
*  Add the necessary values to chip.h to enable values to come from
   the mainboard's devicetree.cb file
*  Add the parameters to the mainboard's devicetree.cb file
*  Locate the platform configuration database file (pdat.bin)
*  Copy the data values from the chip_info structure into the UPDs
*  Display the UPD values

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Edit .config file and add the following lines:
   *  CONFIG_DISPLAY_UPD_DATA=y
*  Testing successful when the UPD data is displayed before the call to
   MemoryInit

Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13896
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2016-03-08 18:06:12 +01:00
Daisuke Nojiri a1bb091d00 archive: build archive tool with HOSTCC
BUG=chromium:502066
BRANCH=tot
TEST=Tested on Jerry

Change-Id: Ic227287784bd0c76a0c4c20a40c581d37420b98c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1b4e818e91998135288978c6cb68a63288bb20e5
Original-Change-Id: I28f5decabcbaf1e61c9b4e549b11e568dace8c09
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312902
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12926
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08 17:40:05 +01:00
Daisuke Nojiri a5ae62e9d2 util: add archive tool
'archive' concatenates files into a single binary blob. Files are
indexed by the base names. See archive.h for the format description.

BUG=chromium:502066
BRANCH=tot
TEST=Tested on Glados

Change-Id: Iea108160e65c8c7bd34c02af824a77cb075ee64b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 21a9ba860f29599ac029f8d49d32399c4e3a73a8
Original-Change-Id: I46b4efb339e3a1e05772ae752f2861026ca09cfc
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311200
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://review.coreboot.org/12925
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-03-08 17:39:38 +01:00
Andrey Petrov 491c016d77 soc/intel/apollolake: Add cbmem_top() implementation
On Apollolake CPU memory mapping is similar to previous SoC, and
we place CBMEM right under TSEG.

Change-Id: I606f690449ba98af6e9fc3074d677c7287892164
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13883
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-03-08 17:28:45 +01:00
Stefan Reinauer 41aa8bc9ab Kconfig: Remove unneeded UDELAY_IO redeclaration
UDELAY_IO is defined in src/cpu/x86/Kconfig, so it does
not need to be redefined in the AMD cpu or board Kconfigs.

Change-Id: I6676881c0ba5d1634230fc3d3c37da3afbc6fceb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13780
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-03-08 16:53:26 +01:00
Aaron Durbin e63be8971b cpu/x86/mtrr: add helper function to detect variable MTRRs
The current MTRR API doesn't allow one to detect variable MTRRs
along with handling fixed MTRRs in one function call. Therefore,
add x86_setup_mtrrs_with_detect() to perform the same actions
as x86_setup_mtrrs() but always do the dynamic detection.

Change-Id: I443909691afa28ce11882e2beab12e836e5bcb3d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13935
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-03-08 16:46:16 +01:00
Lee Leahy e99e2b65cf soc/intel/quark: Add the UPD support for SiliconInit
Add the routines to handle the UPDs for SiliconInit.  Currently no
support is required.

Testing on Galileo:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file:
   *  Add "select ADD_FSP_PDAT_FILE"
   *  Add "select ADD_FSP_RAW_BIN"
   *  Add "select ADD_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
   CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
   UEFIPAYLOAD.fd
*  Edit .config file and add the following lines:
   *  CONFIG_DISPLAY_UPD_DATA=y
*  Testing successful if coreboot calls SiliconInit

Change-Id: I5176ab4b1ea7681c3095f102a86f4b614366c0fc
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13897
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-03-08 16:40:40 +01:00