Commit Graph

15031 Commits

Author SHA1 Message Date
Kyösti Mälkki 05b65ab23a AGESA: Drop DIMM_SUPPORT, _DDR3 and _REGISTERED
Not referenced anywhere.

Change-Id: I57180ccfab93e45df9982d08bad71834a04eb9f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10280
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-23 11:07:28 +02:00
Lee Leahy 77ff0b1a01 Braswell: Use Baytrail as Comparison Base
Add baytrail source for comparison with Braswell.

BRANCH=none
BUG=None
TEST=None

Change-Id: I5170addf41676d95a3daf070a32bcee085f8156d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10117
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-23 01:40:57 +02:00
Lee Leahy b5ad827ee5 drivers/intel: Update FSP 1.1 Driver
Update the FSP driver files from 1.0 to 1.1.

Updates will occur manually to these files only for FSP 1.1 support.  An
fsp_x_y should be added in the future to support newer versions of the
FSP specification.

Please note that due to the interface with EDK2, these files make
references to data structures and fields that use CamelCase.

BRANCH=none
BUG=None
TEST=Build for Braswell or Skylake boards using FSP 1.1.

Change-Id: I2914c047d786a3060075356783ac9758bc41f633
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10049
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-23 01:33:31 +02:00
Patrick Georgi 65ff63f5ea MAINTAINERS: grab build system responsibility
Since nobody else stepped up, I hereby claim responsibility for the
build system.

Change-Id: I580b906d15fc2f049f0072e7b4608b1f19db83ab
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/10277
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-22 22:47:03 +02:00
Vladimir Serbinenko 11b01a9574 Kill ENABLE_TPM.
It's used only in P470 and lynxpoint machines. Remove it from other
southbridges. New machines should use src/drivers/pc80/tpm.

Change-Id: I4741e76df4c6204d65562f016abac9ed60558432
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10268
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-21 20:50:49 +02:00
Patrick Georgi b890a1228d Remove address from GPLv2 headers
As per discussion with lawyers[tm], it's not a good idea to
shorten the license header too much - not for legal reasons
but because there are tools that look for them, and giving
them a standard pattern simplifies things.

However, we got confirmation that we don't have to update
every file ever added to coreboot whenever the FSF gets a
new lease, but can drop the address instead.

util/kconfig is excluded because that's imported code that
we may want to synchronize every now and then.

$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, *MA[, ]*02110-1301[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 59 Temple Place[-, ]*Suite 330, Boston, MA *02111-1307[, ]*USA:Foundation, Inc.:" {} +
$ find * -type f -exec sed -i "s:Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.:Foundation, Inc.:" {} +
$ find * -type f
	-a \! -name \*.patch \
	-a \! -name \*_shipped \
	-a \! -name LICENSE_GPL \
	-a \! -name LGPL.txt \
	-a \! -name COPYING \
	-a \! -name DISCLAIMER \
	-exec sed -i "/Foundation, Inc./ N;s:Foundation, Inc.* USA\.* *:Foundation, Inc. :;s:Foundation, Inc. $:Foundation, Inc.:" {} +

Change-Id: Icc968a5a5f3a5df8d32b940f9cdb35350654bef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/9233
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-05-21 20:50:25 +02:00
Vladimir Serbinenko 537283ddc5 lenovo: Remerge smbios_mainboard_bios_version.
Change-Id: I8df5b7f6707957b925f7bb4dc06a717252c70868
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10275
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
2015-05-21 10:34:38 +02:00
Paul Menzel 54e6aa7216 util/board_status: Fetch and rebase after failed push
Currently, when the remote master branch of the board-status
repository changes between cloning and pushing, `git push origin`
fails.

This race condition happens quite often with REACTS testing commits at
the same time on different systems.

If that happens, just download the objects and refs from the
board-status repository and rebase the local changes on it. Try that
three times before exiting with an error message.

Change-Id: I628ebce54895f44be6232b622d56acbcc421b847
Helped-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Helped-by: Patrick Georgi <pgeorgi@google.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10262
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-21 07:57:48 +02:00
Patrick Georgi 16c12c0a30 Remove unused functions
acpi_fill_slit and acpi_fill_srat were removed in commit 5e597572e.
Take care of the boards that were added in the mean time.

Change-Id: I907e51de5d4ce9acfcce82e6bb30eefff312d35d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10266
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-05-21 07:56:57 +02:00
Paul Menzel 749e075ef3 util/board_status: Add `echo` before message string
Fix up commit 1b6e7a67 (Updates to the board status script) forgetting
to put `echo` in front of the string.

Change-Id: I7d4dfcc62545dfee2073410ba47489318a9bf5c6
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/10265
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-20 23:27:51 +02:00
Vladimir Serbinenko 5e597572ef acpi: make fill_slit and fill_srat into arguments.
SLIT and SRAT are created this way only on amdk8 and amdfam10.
This saves the need of having a lot of dummies.

Change-Id: I76d042702209cd6d11ee78ac22cf9fe9d30d0ca5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7052
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-20 19:51:40 +02:00
Aaron Durbin b4ae5fd107 riscv: enable function and data sections
Every other arch we support has these options enabled.
Enable it to make everything a lot easier in compiling common
code.

Change-Id: I86205468bbd793fbd377e471a1d32be617af5302
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10258
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-20 19:39:14 +02:00
Vladimir Serbinenko cedfb3270c Remove noop smihandler.c in several mainboards.
Change-Id: I14e381e1f1c825699063ca3df20e450f7510b040
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10263
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-20 18:38:01 +02:00
Vladimir Serbinenko 4141b47b07 bd82x6x: Merge common apmc finalize procedure.
Change-Id: I9c938b8a69479fae6b0eb99d1135f1caaf26d0e2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10227
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-20 15:46:56 +02:00
Patrick Georgi eec8dfb5e7 build system: use archives, not linker action to shorten command lines
Intermediate linking may distort linker behavior (in particular related to
weak symbols). The idea is that archives are closer to 'just a list of
object files', and ideally makes the linker more predictable.

Using --whole-archive, the linker doesn't optimize out object files just
because their symbols were already provided by weak versions. However it
shouldn't be used for libgcc, because that one has some unexpected side-effects.

Change-Id: Ie226c198a93bcdca2d82c02431c72108a1c6ea60
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10139
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2015-05-20 08:03:06 +02:00
Matt DeVillier 18fed3dda6 superio/nuvoton: Add support for Nuvoton NCT6779D
Add support for Nuvoton NCT6779D, using NCT6776 as a baseline

Change-Id: I020a21267f7e30bdea4bb5f83d67bd94082fdf05
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/10232
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-05-19 22:36:08 +02:00
Patrick Georgi a6b4798ac0 intel/haswell: Drop MONOTONIC_TIMER_MSR
The variable was set on all haswell boards, so we can do it like on
broadwell where the MSR based timer is assumed to be around, too.

Change-Id: Id48ad7454d4cf83c3b1616b64687cdcfee4baa10
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10256
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-05-19 22:08:32 +02:00
Patrick Georgi e2b0affd6c Remove Kconfig variable that has no effect
DYNAMIC_CBMEM is only selected a couple of times but never declared
or read. Remove it.

Change-Id: I5016dac2c935d3f261001e9f388a8989540e93ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10255
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-05-19 22:08:13 +02:00
Patrick Georgi 342535cc58 Remove Kconfig variable that has no effect
MAINBOARD_HAS_BOOTBLOCK_INIT is only declared once and selected elsewhere
(with no overlap), and never read. Remove it.

Change-Id: Ica1f16182b556dbf4a3b747237af74bcc4c0608c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10254
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-05-19 22:08:06 +02:00
Patrick Georgi a6225fa0cf Remove Kconfig variable that has no effect
CPU_HAS_BOOTBLOCK_INIT is only declared once and selected elsewhere
(with no overlap), and never read. Remove it.

Change-Id: I3f294b0724a87876a7e2f274e6933fe10321a69d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10253
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-05-19 22:07:59 +02:00
Julius Werner da3a146cae arm64: Make SPSR exception masking on EL2 transition explicit
The configuration of SPSR bits that mask processor exceptions is kinda
oddly hidden as an implict part of the transition() function right now.
It would be odd but not impossible for programs to want to be entered
with enabled exceptions, so let's move these bits to be explicitly set
by the caller like the rest of SPSR instead.

Also clear up some macro names. The SPSR[I] bit is currently defined as
SPSR_IRQ_ENABLE, which is particularly unfortunate since that bit
actually *disables* (masks) interrupts. The fact that there is an
additional SPSR_IRQ_MASK definition with the same value but a different
purpose doesn't really help. There's rarely a point to have all three of
xxx_SHIFT, xxx_MASK and xxx_VALUE macros for single-bit fields, so
simplify this to a single definition per bit. (Other macros in
lib_helpers.h should probably also be overhauled to conform, but I want
to wait and see how many of them really stay relevant after upcoming
changes first.)

BRANCH=None
BUG=None
TEST=None

Change-Id: Id126f70d365467e43b7f493c341542247e5026d2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 715600c83aef9794d1674e8c3b62469bdc57f297
Original-Change-Id: I3edc4ee276feb8610a636ec7b4175706505d58bd
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/270785
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10250
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19 20:35:10 +02:00
Julius Werner 745a75faac arm64: Add support for using ARM Trusted Firmware as secure monitor
This patch adds support for integrating the runtime-resident component
of ARM Trusted Firmware (github.com/ARM-software/arm-trusted-firmware)
called BL31. It expects the ARM TF source tree to be checked out under
$(top)/3rdparty/arm-trusted-firmware, which will be set up in a later
patch.

Also include optional support for VBOOT2 verification (pretty hacky for
now, since CBFSv1 is just around the corner and will make all this so
much better).

BRANCH=None
BUG=None
TEST=Booted Oak with ARM TF and working PSCI (with additional platform
patches).

Change-Id: I8c923226135bdf88a9a30a7f5ff163510c35608d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a1b3b2d56b25bfc1f3b2d19bf7876205075a987a
Original-Change-Id: I0714cc10b5b10779af53ecbe711ceeb89fb30da2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/270784
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10249
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19 20:35:03 +02:00
Julius Werner bbca3a9cfa arm64: Reorganize payload entry code and related Kconfigs
This patch slightly reorganizes arm64/boot.c with the aim of being more
readable:
Make more obvious that there's no code execution here after payload_entry.

[pg: taken from patch linked below]

Change-Id: Ia341e5d290b10ad5ba3edb349b8a7f619022d99f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e
Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/270783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10247
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19 20:34:55 +02:00
Julius Werner 883ec987a6 arm64: Reorganize payload entry code and related Kconfigs
This patch slightly reorganizes arm64/boot.c with the aim of being more
readable: we need to sync the i-cache in both code paths, so do it in
a single location.

[pg: taken from patch linked below]

Change-Id: Iab173acfc6d66e4dccb6f6ab916aea2007632bfd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e
Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/270783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10246
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19 20:34:38 +02:00
Julius Werner b436ce1ac6 arm64: Reorganize payload entry code and related Kconfigs
This patch slightly reorganizes arm64/boot.c with the aim of being more
readable: Make spintable handling optional through a kconfig flag.

[pg: taken from patch linked below]

Change-Id: I64610640835473fcc3d9eff01feb5f861b753eb8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e
Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/270783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10245
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19 20:34:29 +02:00
Julius Werner f52602a740 arm64: Reorganize payload entry code and related Kconfigs
This patch slightly reorganizes arm64/boot.c with the aim of being more
readable. Improve locality of code.

[pg: taken from patch linked below]

Change-Id: Ie9ea6a10b9d5e5c33bf020369afcae4f10ef068e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e
Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/270783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10244
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19 20:34:23 +02:00
Julius Werner 786b122479 arm64: Reorganize payload entry code and related Kconfigs
This patch slightly reorganizes arm64/boot.c with the aim of being more
readable: the secure monitor entry is now guarded by an explicit if
statement for its Kconfig rather than hiding than in the corresponding
header file. This makes it clear that there are two (soon three)
separate code paths here.

Change-Id: I44993da7a982b08f485b93ffc522d193bb3fa118
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e
Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/270783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10243
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19 20:33:40 +02:00
Julius Werner f1df50edf3 arm64: Reorganize payload entry code and related Kconfigs
Rename Kconfig options for secmon and spintable to be prefixed with
ARM64_ instead of ARCH_, which seems to be the standard throughout the
rest of coreboot (e.g. ARM_LPAE or X86_BOOTBLOCK_SIMPLE). I think this
provides a clearer separation between generic options that are selected
by the architecture (e.g. a hypothetical ARCH_HAS_FEATURE_X similar to
some of the MAINBOARD_HAS_... we have) and options that only make sense
in the context of a single architecture.

Change-Id: I38c2efab833f252adbb7b61ef0af60ab25b768b0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e
Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/270783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10242
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19 20:33:28 +02:00
Julius Werner 75515eaa4b arm64: Reorganize payload entry code and related Kconfigs
The secure monitor entry is now guarded by an explicit if
statement for its Kconfig rather than hiding than in the corresponding
header file. This makes it clear that there are two (soon three)
separate code paths here. Similar change for the optional spintable
feature in the "legacy" payload entry path.

[pg: split out from the patch linked below]

Change-Id: Ia1554959b3268b718a9606e2f79d8f22f336c94d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e
Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/270783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10248
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19 20:33:16 +02:00
Julius Werner 59e7b42af7 arm64: Reorganize payload entry code and related Kconfigs
Remove the secmon Kconfig guard from Makefiles that add to the secmon
class since they are redundant (the class is simply not used when
compiling without secmon) to improve readability/ease-of-use.

[pg: taken out of the patch linked below]

Change-Id: I2f0ad8a923ca32fcade748ac8ee50c23cf9bafb9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e
Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/270783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10241
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19 20:33:06 +02:00
Julius Werner 404df44427 arm64: Reorganize payload entry code and related Kconfigs
Reorganize Kconfig (split out from the original patch linked below)

Change-Id: I84ec8e453dd7a3980de95a455ad21494c601a98c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5067e47bc03f04ad2dba044f022716e0fc62bb9e
Original-Change-Id: I1b2038acc0d054716a3c580ce97ea8e9a45abfa2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/270783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10240
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19 20:32:55 +02:00
Patrick Georgi 7b32145763 cbfstool: Copy generated files to the build hierarchy before use
Instead of writing to the source tree (which we should generally avoid),
copy the pre-generated files (from lex and yacc) to $(objutil). Adapt
include paths and rules so they're found.

Change-Id: Id33be6d1dccf9a1b5857a29c55120dcc8f8db583
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10252
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19 20:30:11 +02:00
Patrick Georgi 8d6e24c739 cbfstool: clarify dependencies in Makefile
While logical, make's handling of multiple targets in a rule isn't
intuitive, and was done wrong in cbfstool's Makefile.

%.c %.h: %.l encourages make to run the rule twice, once to
generate the .c file, once for the .h file. Hilarity ensues.

Change-Id: I2560cb34b6aee5f4bdd764bb05bb69ea2789c7d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10251
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-19 20:30:04 +02:00
Kyösti Mälkki d32b27383b cbfstool: Rename autogenerated targets
These names will skip the lint-whitespace tests.

Change-Id: If4ac1f8e11fd0ac62f09696f2704477b6eb30046
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10212
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19 17:03:54 +02:00
Vladimir Serbinenko 428130e839 nehalem native gfx init: Adjust state to be compatible with OPROM.
My main payload is GRUB and I load SeaBIOS as secondary payload when for some
reason I want to boot windows. In this scenario SeaBIOS runs VGA oprom
(SeaVGABIOS is not good enough with intel gfx). VGA oprom expects either
completely uninited gfx or some special state in gmbus and software scratch
registers. Provide this state.

The only alternative without this patch for such usecase is to use oprom and
I'd like to avoid doing so when going my main boot path to GNU/Linux.

Change-Id: Ic157a6a580d7a5048ac28155e0d6b3433bbd1f2c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10239
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19 16:24:40 +02:00
Vladimir Serbinenko 38cf94b250 ivybridge native gfx init: Adjust state to be compatible with OPROM.
My main payload is GRUB and I load SeaBIOS as secondary payload when for some
reason I want to boot windows. In this scenario SeaBIOS runs VGA oprom
(SeaVGABIOS is not good enough with intel gfx). VGA oprom expects either
completely uninited gfx or some special state in gmbus and software scratch
registers. Provide this state.

The only alternative without this patch for such usecase is to use oprom and
I'd like to avoid doing so when going my main boot path to GNU/Linux.

Change-Id: I38e78fb845e43b81df084cd4d65f4618bfb2506d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10205
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19 16:24:05 +02:00
Vladimir Serbinenko 3387e4e770 gma/edid: Fix gma register access.
0x20 was incorrectly represented as 4 * 5 while in fact it's 4 * 8

Change-Id: I6053a3baa6de0da9f1d648009353bc1fe542f81f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10237
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19 16:23:32 +02:00
Vladimir Serbinenko 4679c41db2 Move smi trap sample to documentation, don't keep it in every mobo.
Sample code belongs to documentation, not copied 100x over prodcution code.

Change-Id: I6bb318d76057d02bd6ac5641d12d56ab6d60b745
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10229
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19 16:22:56 +02:00
Vladimir Serbinenko a5dc9f1be8 Remove useless extern gnvs declaration in smi handlers.
Change-Id: I3047badea8d4f61155f4e4f7d3d078426948162a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10228
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19 16:22:24 +02:00
Aaron Durbin 89d17bb087 vboot: remove vboot_context.h
The vboot_context.h file hasn't been used since commit
6d65f796db.  Remove it.

Change-Id: I57a6c619c6e1f57be6963da2954329bc9c007dd8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10223
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19 15:16:51 +02:00
Vladimir Serbinenko c728288a1f nvramcui: reboot at the end as TODO suggests
Use cf9 to reboot at the end.

Change-Id: I642a5ec89c864fb03bbcdf6e4fcbb1e28f3fc34c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4693
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19 15:15:22 +02:00
Kyösti Mälkki 017c2150d4 pcengines/apu1: Add switch between UART and GPIO modes
These are alternative customer options connected to J19 header.
We need to avoid modifying devicetree.cb, so we fix devicetree
for the super-io device-enables at runtime instead.

Change-Id: I04a79974b9bdf52b09ffc1b1362e201eab1ee011
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10178
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19 14:46:58 +02:00
Aaron Durbin 58d5e21851 x86: garbage collect SMM programs
The non-module SMM programs were not being garbage collected
during linking. Do this so that one doesn't have to add dependencies
for unused functions in SMM.

TEST=Interrogated readelf -e smm.elf on both builds as well as diffed
     the symbol table. Runtime testing was not done.

Change-Id: I31991496d92191e540df6340c587eec09c7022b3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10219
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19 10:36:48 +02:00
Aaron Durbin e645bcae7c regions: add more helpers
Fill out functions to get the offset and size for both
regions and region_devices. Additionally add a helper for
memory mapping an entire region_device.

Change-Id: I8896eaf5b29e4a67470f4adc6f5b541566cb93b5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10215
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-05-19 10:36:43 +02:00
Kyösti Mälkki c877149e9d cbfstool: Fix fmd_scanner build compatibility
Fixes these errors:
error: declaration of ‘input’ shadows a global declaration [-Werror=shadow]
error: redundant redeclaration of ‘isatty’ [-Werror=redundant-decls]

Change-Id: I4563d36e5389db4fdc5be3ca4e0e88af2642f7f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10162
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Sol Boucher <solb@chromium.org>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
2015-05-19 07:17:36 +02:00
Timothy Pearson df699d545f util/cbmem: Update cbmem utility to parse the new IMD structures
This resolves the cbmem table of contents access failure introduced
in commit 0dff57dd.

Change-Id: Ie143ae11d97f26bd17fe10e1382fae9e5ad1a60e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/10236
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-05-18 17:50:30 +02:00
Yidi Lin 7267ccbae8 libpayload: add mediatek timer driver
Change-Id: Ifb19cf97d4db6c7394521e549968a0cfb6ed1c75
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0137652ca07e290bb3cb1cc82a00b44ac7bcc7bf
Original-Change-Id: Ica649927d3533c847b24e520e8fe73d75fb9e786
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/257375
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/10170
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-18 13:20:00 +02:00
Joseph Lo 589e63ee7c drivers/gic: reprogram the GIC CPU interface to bypass IRQ
GICv2 provides a wake IRQ/FIQ (for wake-event purpose), which are not
disabled by GIC CPU interface. This is done by adding a bypass override
capability when the interrupts are disabled at the CPU interface. To
support this, there are four bits about IRQ/FIQ BypassDisable in CPU
interface Control Register. So the CPU can exit from WFI when an
asserted IRQ is coming. This is critical for power gating a CPU.

BRANCH=none
BUG=chrome-os-partner:39620
TEST=testing with CPU idle with power down state support and CPU can
     wake up normally

Change-Id: I71ac642e28024a562db898665b74a5791fce325a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3a3f098cbf3fbfdab8150ebd4fd688fdb472b529
Original-Change-Id: I20569a18f34a4b11b8c8c67ea255b3d0f021839f
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/269116
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10172
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-18 13:16:33 +02:00
Joseph Lo b7d0ffd1ed arm64: psci: add cpu_suspend support
Implement the cpu_suspend for the PSCI service in secmon.

BRANCH=none
BUG=chrome-os-partner:39620
TEST=test with CPU idle driver that invoke the cpu_suspend of PSCI

Change-Id: I4cdfab88bf36bf432fb33c56c1ea114b384528f8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 90b3ea3fcb21cb393e30a8359f0328054961f6d5
Original-Change-Id: Ieb76abc017b9c3e074cc018903cef72020306a8f
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/269115
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/10171
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-18 13:16:26 +02:00
Kyösti Mälkki 2e0425986f cbfstool: Fix shadowed global index
Change-Id: Ic8bccea1f2ddef874d8e440fa4fa05de1d4f9550
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10210
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-05-17 16:05:08 +02:00