Some EABI conformant toolchains like GCC need additional functions like raise.
To prevent payloads adding arch-specific implementations everywhere, we should
provide the default version in libpayload.
BUG=none
TEST=emerge-nyan libpayload # pass
BRANCH=none
Original-Change-Id: Id1e3c29590aa5881aefd944a7551949ce9a47b8f
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199686
(cherry picked from commit 395810c4b744dbb720050f79a2c1a30e81464554)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2e1d8c8cb519f8e788c22d081132d23b49b8f822
Reviewed-on: http://review.coreboot.org/7906
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
I always thought the support for multiple logical SCSI units in the USB
mass storage class was a dead feature. Turns out that it's actually used
by SD card readers that provide multiple slots (e.g. one regular sized
and one micro-SD). Implementing perfect support for that would require a
major redesign of the whole MSC stack, since the one device -> one disk
assumption is deeply embedded in our data structures.
Instead, this patch implements a poor man's LUN support that will just
cycle through all available LUNs (in multiple calls to usb_msc_poll())
until it finds a connected device. This should be reasonable enough to
allow these card readers to be usable while only requiring superficial
changes.
Also removes the unused 'protocol' attribute of usb_msc_inst_t.
BRANCH=rambi?,nyan
BUG=chrome-os-partner:28437
TEST=Alternatively plug an SD or micro-SD card (or both) into my card
reader, confirm that one of them is correctly detected at all times.
Original-Change-Id: I3df4ca88afe2dcf7928b823aa2a73c2b0f599cf2
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/198101
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 960534a20e4334772c29355bb0d310b3f41b31ee)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I39909fc96e32c9a5d76651d91c2b5c16c89ace9e
Reviewed-on: http://review.coreboot.org/7904
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
So I was debugging this faulty USB SD card reader that would just fail
it's REQUEST SENSE response for some reason (sending the CSW immediately
without the data), cursing those damn device vendors for building
non-compliant crap like I always do... when I noticed that we do not
actually set the Allocation Length field in our REQUEST SENSE command
block at all! We set a length in the CBW, but the SCSI command still has
its own length field and the SCSI spec specifically says that the device
has to return the exact amount of bytes listed there (even if it's 0). I
don't know what's more suprising: that we had such a blatant bug in this
stack for so long, or that this card reader is really the first device
to actually be spec compliant in that regard.
This patch fixes the bug and changes the command block structures to be
a little easier to read (why that field was called 'lun' before is
beyond me... LUN is a transport level thing and should never appear in
the command block at all, for any command). It also fixes a memcpy() in
wrap_cbw() to avoid a read buffer overflow that might expose stack frame
data to the device.
BRANCH=rambi?,nyan
BUG=chrome-os-partner:28437
TEST=The card reader works now (for it's first LUN at least).
Original-Change-Id: I86fdcae2ea4d2e2939e3676d31d8b6a4e797873b
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/198100
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 88943d9715994a14c50e74170f2453cceca0983b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I3097c223248c07c866a33d4ab8f3db1a7082a815
Reviewed-on: http://review.coreboot.org/7903
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Always build CBMEM for romstage, even for boards that will not use it.
We further restrict car_migrate_variables() runs to non-ROMCC boards without
BROKEN_CAR_MIGRATE.
This fixes regression of commit 71b21455 that broke CBMEM console support
for boards with a combination of !EARLY_CBMEM_INIT && !HAVE_ACPI_RESUME.
Change-Id: Ife91d7baebdc9bd1e086896400059a165d3aa90f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7877
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored
and was not correctly set on affected sockets and boards. It was still
referenced in romstage linker script. This was discovered by clang builds
failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed.
The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken
from intel/cpu/cache_as_ram.inc.
Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7887
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Disable Super I/O related topics showing in menuconfig.
Change-Id: I246bc935147baf6ff2dfcb306079cc2d4c7cb153
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7985
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
make called within make prints 'Entering directory'
cruft which confuses the architecture support test.
Silence it.
Change-Id: I7ce7e0ff49e9317fe736ed80f5f18186d416ae63
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/7968
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
If it's a 4 byte format (as per documentation), there
are some reserved bits, so let's mark them as such...
Unfortunately undone while upstreaming changes.
Change-Id: I50f12cfff2c9bb9d082a5f3c3ac54c0d514d862c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Originally-Reviewed-on: http://review.coreboot.org/7674
Reviewed-on: http://review.coreboot.org/7964
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The "((1ull << (sizeof(modules) * 8)) - 1)" statement evaluates to
0xffffffff, but there's no need to AND with that value, as 'modules'
is already 32-bit. The '&&' is most likely a typo, which meant bitwise
and, as indicated by the structure of thus operation.
Remove this superfluous statement. This also fixes a clang warning.
Change-Id: Ie55bd9f8b0ec5fd41e440f56dcedd40c830bf826
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7965
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Regression in commit 88ca81a caused UPDATE-FIT step to no longer run when
microcode was added to CBFS.
Change-Id: I6ea4b6b6a8de598be810c930baa497f8c7fdc4b8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7959
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
CPU_MICROCODE_CBFS_LOC used a non-existing dependency variable
CPU_MICROCODE_IN_CBFS. This broke alignment of microcode in CBFS.
Remoce CPU_MICROCODE_CBFS_LOC from global namespace as it is only
used with PLATFORM_FSP.
CPU_MICROCODE_CBFS_LEN was no longer used at all.
Change-Id: I0454397924d2526d97b1f095cc371ba962873c99
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7957
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
After relocation the weak symbol map_oprom_vendev is no longer NULL.
Always have empty stub function defined.
Change-Id: I5b1bdeb3f37bb04363cf3d9dedaeafc9e193aaae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7956
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
After relocation the weak symbols are no longer NULL.
Always have empty stub function defined.
Change-Id: I6cb959c1fa10b4b63018e400636842e2a15d6e81
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7955
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
We had NULL reference with cache_loaded_ramstage() if
CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM was not set so boot never
proceeded to ramstage.
Cache implementation outside CBMEM provides means for platform-specific
location so there is no need of weak attributes here.
Change-Id: I1eb1a713896395c424fde23252c374f9065fe74d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7954
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Commit bb932c56 (nyan*: I2C: Implement bus clear when 'ARB_LOST' error
occurs) unintentionally reverted commit 16472743 (3dparty: Update to
latest commit in blobs repository).
Apply that commit again:
'blobs' now contains updates which allow binary AGESA to build with
Clang. Pull those in, in anticipation of re-enabling -Werror on Clang
builds.
Change-Id: I2530b6c58d369f1741b1a77bdfd7bcdb64ac9feb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7963
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
It's not needed, as we can use a simpler macro instead.
Change-Id: Ib96f5cfa434d0383ee3bfe49995a8f8830987f20
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7925
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
This change updates the cfg file for Micron/Samsung 2GB,
792MHz DRAM based on the data generated by t124_emc_reg_tool.
BUG=none
BRANCH=blaze
TEST=emerged coreboot, booted successfully into kernel.
Original-Change-Id: I840cdd967c3b38479946a497a91da89bef5a98ad
Original-Signed-off-by: Jerry Wang <jerryw@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/199296
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit cb70674c6551c8c36d2fd2d220e0f677ed2c6b24)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I11222bc1453a76cc27c2be169be5d3481ed7cfe7
Reviewed-on: http://review.coreboot.org/7902
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
When a watchdog reset happens, the SOC will reset but other parts of the
system might not. That puts the machine in a funny state and may prevent it
from booting properly.
BUG=chrome-os-partner:28559
TEST=Built for nyan, nyan_big and nyan_blaze. Booted normally, through EC
reset, software reset ("reboot" command from the terminal), and through watch
dog reset. Verified that the new code only triggered during the watchdog reset
and that the system rebooted and was able to boot without going into recovery
mode unnecessarily.
BRANCH=nyan
Change-Id: Id92411c928344547fcd97e45063e4aff52d2e9e8
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/198582
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit b298be41c0959c58aeb8be5bf15141549da2504c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7900
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
When a watchdog reset happens, the SOC will reset but other parts of the
system might not. In order to detect those situations we can check the
rst_status register in the PMC.
BUG=chrome-os-partner:28559
TEST=With this and a change which uses the new function in the nyan boards,
built for nyan, nyan_big and nyan_blaze. Booted normally, through EC reset,
software reset ("reboot" command from the terminal), and through watch dog
reset. Verified that the new code only triggered during the watchdog reset and
that the system rebooted and was able to boot without going into recovery mode
unnecessarily.
BRANCH=nyan
Original-Change-Id: I7430768baa0304d4ec8524957a9cc37078ac5a71
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/198581
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 5fdc0239fc2960167dd9c074f3804bf9e4ad686a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5845d3a4d819868f5472c758e83e83b00e141b72
Reviewed-on: http://review.coreboot.org/7899
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
The original sdram-hynix-2GB-792.inc was just copied from nyan
bct file. This change updates the cfg file for Hynix 2GB, 792MHz
DRAM based on the data generated by t124_emc_reg_tool.
BUG=none
BRANCH=blaze
TEST=emerged coreboot, booted successfully into kernel.
Original-Change-Id: I9534b4df6d35193179de124309df12ed830098a0
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197660
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 797dabe54f2679bb5717961dda1947df453eb0f1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie67bedb29d5d9c3a3b58d949ddf9600716c385ec
Reviewed-on: http://review.coreboot.org/7898
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This is a fix for the 'Lost arb' we're seeing on Nyan* during
reboot stress testing. It occurs when we are slamming the
default PMIC registers with pmic_write_reg().
Currently, I've only captured this a few times, and the bus
clear seemed to work, as the PMIC writes continued (where
they'd hang the system before bus clear) for a couple of regs,
then it hangs hard, no messages, no 2nd lost arb, etc. So
I've added code to the PMIC write function that will reset the
SoC if any I2C error occurs. That seems to recover OK, i.e. on
the next reboot the PMIC writes all go thru, boot is OK, kernel
loads, etc.
BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Tested on nyan. Built for nyan and nyan_big.
Original-Change-Id: I1ac5e3023ae22c015105b7f0fb7849663b4aa982
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197732
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit f445127e2d9e223a5ef9117008a7ac7631a7980c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I584d55b99d65f1e278961db6bdde1845cb01f3bc
Reviewed-on: http://review.coreboot.org/7897
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reduce difference with exynos5420/clock.c by fixing some whitespace
and an include directive.
Change-Id: Ifbdd61c8300f3988f5f729fe7d6124ac8a9b7821
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7926
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Commit 5839635a broke cbfs file-position, probably resulting with
non-booting Intel platforms using mrc.bin and the risk of AGESA
with HAVE_ACPI_RESUME corrupting cbfs as s3nv.bin was not properly
located.
Change-Id: I6ca7a3cdf8dfe40bf47da6c6071ef7b1f42a32b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7920
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We recently changed the USB stack to detach devices aggressively that we
don't intend to use. This alone is not really a problem, but it
exarcerbates the fact that our device detachment itself is not very
good. We destroy any local info about the device, but we don't properly
disable the offending port. The device keeps thinking that it's active,
and if we later try to reuse that device address for another device
things become confused.
The real fix would be to properly disable all ports that we don't intend
to use. Unfortunately, this isn't really possible in our current
device/hub polymorphism structure, and I don't want to hack a new
disable_port() callback into usbdev_t that really doesn't belong there.
We will only be able to fix this cleanly after we ported all root hubs
to the generic_hub interface.
Until then, an easy workaround is to just avoid reusing addresses as
long as possible. This is firmware, so the chance that we'll ever run
through 127 devices is really small in practice. Even if we ever fix the
underlying issue, it's probably a smart precaution to keep.
BRANCH=nyan,rambi
BUG=chrome-os-partner:28328
TEST=Boot from a hub that has an "unknown" device in an earlier port
than the stick you want to boot from, make sure you can still boot.
Original-Change-Id: I9b522dd8cbcd441e8c3b8781fcecd2effa0f23ee
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197420
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 28b48aa69b55a983226edf2ea616f33cd4b959e2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id4c5c92e75d6b5a7e8f0ee3e396c69c4efd13176
Reviewed-on: http://review.coreboot.org/7881
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The console output driver framework in libpayload is currently built on
the putchar primitive, meaning that every driver's function gets called
one character at a time. This becomes an issue when we add drivers that
could output multiple characters at a time, but have a high constant
overhead per invocation (such as the planned GDB stub, which needs to
wrap a special frame around output strings and wait for an
acknowledgement from the server).
This patch adds a new 'write' function pointer to the
console_output_driver structure as an alternative to 'putchar'. Output
drivers need to provide at least one of the two ('write' is preferred if
available). The CBMEM console driver is ported as a proof of concept
(since it's our most performace-critical driver and should in theory
benefit the most from less function pointer invocations, although it's
probably still negligible compared to the big sprawling mess that is
printf()).
Even with this fix, the problem remains that printf() was written with
the putchar primitive in mind. Even though normal text already contains
an optimization to allow multiple characters at a time, almost all
formatting directives cause their output (including things like
padding whitespace) to be putchar()ed one character at a time.
Therefore, this patch reworks parts of the output code (especially
number printing) to all but remove that inefficiency (directives still
invoke an extra write() call, but at least not one per character). Since
I'm touching printf() core code anyway, I also tried to salvage what I
could from that weird, broken "return negative on error" code path (not
that any of our current output drivers can trigger it anyway).
A final consequence of this patch is that the responsibility to prepend
line feeds with carriage returns is moved into the output driver
implementations. Doing this only makes sense for drivers with explicit
cursor position control (i.e. serial or video), and things like the
CBMEM console that appears like a normal file to the system really have
no business containing carriage returns (we don't want people to
accidentally associate us with Windows, now, do we?).
BUG=chrome-os-partner:18390
TEST=Made sure video and CBMEM console still look good, tried printf()
with as many weird edge-case strings as I could find and compared serial
output as well as sprintf() return value.
Original-Change-Id: Ie05ae489332a0103461620f5348774b6d4afd91a
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196384
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit ab1ef0c07736fe1aa3e0baaf02d258731e6856c0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I78f5aedf6d0c3665924995cdab691ee0162de404
Reviewed-on: http://review.coreboot.org/7880
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use 'd' instead of 'hhd' when printing absolute year of manufacture. This
is the correct type in this case, as the result is autoatically promoted
to int.
Change-Id: Ice4155bb1a04f206ae55c45c260089d6971b77d1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7885
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
'blobs' now contains updates which allow binary AGESA to build with clang.
Pull those in, in anticipation of re-enabling -Werror on clang builds.
Change-Id: I734de0b93ebc1e78781f1d5f48e280badc3cf8b3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7884
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Callout FCH_OEM_CONFIG is made during AMD_INIT_RESET, so it was required
to provide GetBiosCallOut here too.
Change-Id: I0eab858677d14536293385ca37daab3e538132e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7826
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
We should potentially provide an OEM platform hook to manipulate parameters
around any entry point to AGESA. Use structure for such ops to avoid weak
functions and lots of empty function stubs.
Change-Id: I99bf7de8a1e2f183399d2216520a45d0c24fd64c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7824
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
It does not really matter if we continue or return after a failed
assertion, system configuration is invalid anyway.
Change-Id: I5ba47ee3fd6c5ff97b9229f8bfc9db08873b08ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7823
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Not part of wrapper to AGESA, but workaround for enable_resources().
Also remove remains of comments in non-fam14 wrappers.
Change-Id: I2526821ca283feb6a506b602b86f817f8b03b341
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7816
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
These are not wrappers for AGESA as they do not enter vendorcode at all.
We expect most of the added fixme.c file to be written without use of AMDLIB.h
and parts relocated as northbridge enable_resources().
Change-Id: Iba6d59e2a7672349208e9a65fcd2cb1094ab7d50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7815
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Hung-Te Lin