Commit Graph

35227 Commits

Author SHA1 Message Date
Duncan Laurie ab673cee08 security/tpm: Change wording of variable names
Change the name of these variables to 'allowlist'.

Change-Id: I9d5553988a1c9972b8f1ebaeee20878b23a8aa9b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42316
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 21:36:02 +00:00
Kyösti Mälkki c7e2b6d140 lib/reg_script: Add guards for <arch/io.h>
Header and implementation only present for ARCH_X86 stages.

Change-Id: I4b28e666a8a60bd0365cda8d7affa1eb063c4690
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42416
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 21:13:36 +00:00
Kyösti Mälkki 7336f97deb treewide: Replace CONFIG(ARCH_xx) tests
Once we support building stages for different architectures,
such CONFIG(ARCH_xx) tests do not evaluate correctly anymore.

Change-Id: I599995b3ed5c4dfd578c87067fe8bfc8c75b9d43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42183
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 21:13:09 +00:00
Furquan Shaikh 5edbb1c5d9 Revert "soc/amd/picasso: Reconfigure SPI speeds after FSP-S has run"
This reverts commit d5f1e0f973.

Reason for revert: FSP-S is now fixed to not touch the SPI
configuration registers. Thus, coreboot does not need to reconfigure
SPI after FSP-S has run.

BUG=b:153506142
TEST=Verified that SPI configuration registers look the same before
and after FSP-S has run. em100 works fine without any additional
changes in coreboot to reconfigure SPI.

Change-Id: I4832e62e0331aa39abe0cca7725915262bb2cf83
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-17 20:54:32 +00:00
Duncan Laurie 3cd3cb6f33 ec/google/wilco: Suppress UCSI events in S0ix
If a UCSI event comes in when the EC is in S0ix mode then the kernel
driver attempts a transaction but fails and this can leave the system
in an unexpected state where the only wake source is the power button.

This change will not notify the UCSI driver if the EC is in S0ix mode
and instead keep track of the event and send it on resume.

BUG=b:157923800
TEST=tested on drallion system:
1. Put drallion system into suspend
2. Attach power supply
3. Ensure the system can wake with keypress

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I43acb089385d9b41ac955f053e409daad67423f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-17 19:46:36 +00:00
Nick Vaccaro 6f2f236862 mb/google/volteer: remove unused GPP_H23
BUG=b:157567939
TEST="emerge-volteer coreboot chromeos-bootimage", flash and
boot volteer to kernel.

Change-Id: I3046cf3a359e833a5d204f78ab84312e8665061f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42411
Reviewed-by: Jes Klinke <jbk@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 19:46:28 +00:00
Brandon Breitenstein c9a3451305 mb/volteer: Set IomTypeCPortPadCfg default to 0x09000000
Temporary workaround for S0ix issues related to FSP's handling of 0 value.
When IomTypeCPortPadCfg is 0 FSP completely skips any flow related to this
value which seems to be causing issues with s0ix.

This is still being debugged and a final solution will be made when available

BUG=b:159151238
TEST=flash image with workaround to volteer and verify that s0ix
cycles correctly.

Change-Id: Id79dd1c49958389cdb666b3760abd821bc1973a8
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42268
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 19:24:22 +00:00
Felix Held 097e449013 soc/amd/picasso: rename PICASSO_UART Kconfig option
The PICASSO_UART Kconfig option is about using the internal MMIO UART
controllers in Picasso for console, so rename it to PICASSO_CONSOLE_UART

Change-Id: I38ac9ee96af826fe49307b4d0e055a43fcbd4334
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-17 18:52:07 +00:00
Furquan Shaikh ca481ee87f soc/amd/picasso: fix build if PICASSO_UART is unset
This change includes uart.c in bootblock, romstage, ramstage and
verstage unconditionally because this file is handling more than just
the UART console configuration. This allows boards to take advantage
of picasso_uart_mmio_ops even if PICASSO_UART is not selected.
uart_platform_base and uart_platform_refclk mustn't be provided if
PICASSO_UART is unset, so add an #if around those functions.

BUG=b:158346697

TEST=Mandolin builds again.

Change-Id: If1173034b0d2ed32f77241768e1e8abb208aac3a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42339
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 18:51:25 +00:00
Angel Pons 4c466c9c96 device/pnp_ops.h: Use pnp.h functions
With BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.

Change-Id: I3ca080e700cf7b7f5b76cadddc7e41960413433c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42133
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 18:17:09 +00:00
Elyes HAOUAS a0eb64ad33 crossgcc: Upgrade GDB to version 9.2
Change-Id: I30dae356ec3b373ac036c7eced7d6e89ddd08246
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38787
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 16:32:05 +00:00
Elyes HAOUAS 91fb139956 crossgcc: Remove "Make"
In its current state, it draws more dependencies in than it solves
which makes it useless.

Change-Id: I08f592731c3da2ac19e1f93682256f559a067fc4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-17 11:20:30 +00:00
Wonkyu Kim c66c15334a soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD
This patch adds support for enabling/disabling PCIe hot-plug via
a chip config option PcieRpHotPlug, which is copied to the corresponding
FSP-S UPD.

BUG=b:156879564
BRANCH=none
TEST=Boot Volteer/RVP with FSP log and check hotplug enabled/disabled

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I4c0187644b6ca9735f1b159e110e3466af14ff71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41794
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 09:18:45 +00:00
Puthikorn Voravootivat 549a853f8f mb/google/hatch: mushu: Add F75303 temp sensor to dptf
Update the following in dptf.asl
- Add support for TSR3
- Change TSR0/TSR1/TSR2/TSR3
  From: Charger, 5V,  GPU       , None
  To:   Charger, GPU, F75303_GPU, F75303_GPU_POWER
- Adjust fan/cpu trip point accordingly
- Fix formating in dptf.asl
- Throttle charger when TSR0 (charger) is hot instead of throttle CPU

BUG=b:158676970
BRANCH=None
TEST=grep . /sys/class/thermal/thermal_zone5/{type,temp}
/sys/class/thermal/thermal_zone5/type:TSR3
/sys/class/thermal/thermal_zone5/temp:50800

Change-Id: Iedbb6bc7c1e59a027119c70791b9bc8a4d83ff87
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42270
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Bob Moragues <moragues@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 09:18:26 +00:00
Patrick Rudolph 2fdabd9038 smmstore: Verify userspace-provided pointer to protect SMM
Use the introduced functions and verify pointers in the SMMSTORE.
Make sure to not overwrite or leak data from SMM and update the
documentation as well.

Change-Id: I70df08657c3fa0f98917742d8e1a6cb1077e3758
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41085
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 09:18:05 +00:00
Patrick Rudolph 41fec869fb cpu/x86/smm: Add helper functions to verify SMM access
* Add a function to check if a region overlaps with SMM.
* Add a function to check if a pointer points to SMM.
* Document functions in Documentation/security/smm

To be used to verify data accesses in SMM.

Change-Id: Ia525d2bc685377f50ecf3bdcf337a4c885488213
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41084
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-17 09:17:56 +00:00
Patrick Rudolph c59d9e3917 soc/intel/cannonlake/vr_config: Add CFL defaults to TDC powerlimit
Add CFL defaults for VR TDC config and provide Iccmax for additional Xeon
CPUs tested on the Prodrive/Hermes board.

Based on the following Intel documents:
* Document Number 570805 (XEON E EDS Vol 1)
* Document Number 337344 (CFL Datasheet Vol 1)
* Document Number 571264 (CFL CNP PDG)

Change-Id: I681de076318fb647c44cc8b8c42eb297018cc540
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-17 09:17:47 +00:00
Patrick Rudolph 9de8c8013b soc/intel/cannonlake: Use table instead of switch-case
This makes future changes easier to review.

Change-Id: I5d67801a46a1613fbc7f813e94933fa30c1b92df
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-17 09:17:38 +00:00
Patrick Rudolph 802cbee789 ifdtool: Improve PCH strap handling
Read the PCH Strap Length field in FLMAP1 as described in the
"SPI Programming Guide" and print the number of fields specified there.

This code dumps the following straps:
* Intel GM45: 8 straps
* Intel C216: 72 straps
* Intel C240: 360 straps

Add a new function to easily set PCH straps, which is useful for debugging.

Change-Id: Ieb7891b214d82c984379794de9b3fe1a6d0d3466
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-17 09:16:51 +00:00
Shiyu Sun aeacf8b444 mb/google/puff: add MST and LSPCON details to variants devicetree
Added device hid info to the MST and LSPCON devices on
kaisa, duffy and noibat.

BRANCH=None
BUG=b:156546414
TEST=None

Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Change-Id: I7b54512cd88e7280374c188315cabc2fba197f69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-17 09:16:38 +00:00
Angel Pons 2ebea2d427 Revert "x86/lapic: Set EXTINT on BSP only"
This reverts commit aac79e0b8f.

Reason for revert: This massively slows down the boot process because
the LAPIC delivery mode for the APs is not set anymore. Plus, not all
review comments were fully addressed, yet this got merged in anyway.

Change-Id: If9bae6aae0d4d1f21b067a7d970975193c2b16d5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-16 21:17:42 +00:00
Keith Hui 02c565b35a superio/winbond/w83977tf: Add suspend related fields
Add two fields for the ACPI logical device to the ACPI code. They are
used for taking asus/p3b-f board out of suspend by keyboard or mouse.

Change-Id: Icaadfea6a4dce7a2d665e8d89a024359975f8b2c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41096
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16 20:17:26 +00:00
Zheng Bao aac79e0b8f x86/lapic: Set EXTINT on BSP only
When Linux is booted, the kernel reports

    "do_IRQ: 1.55 No irq handler for vector"

So far it comes with payloads SeaBIOS and depthcharge, not with
Grub. We assume Grub does something to avoid this problem.

AMD bug tracker system (JIRA PLAT-21393) says the APs can not be set
EXTINT delivery mode.

In Intel 64 and IA-32 Architectures Software Developer’s Manual volume
3A, see chapter 10.5.1 Local Vector Table, it says:
"The APIC architecture supports only one ExtINT source in a system,
usually contained in the compatibility bridge. Only one processor in the
system should have an LVT entry configured to use the ExtINT delivery
mode."

Tested on mandolin (Picasso) board, the error in dmesg is gone.

The bug 153677727 has two parts.
1. Soft lockup
2. do_IRQ 1.55.
The soft lockup issued has been fixed by
https://review.coreboot.org/c/coreboot/+/41128

BUG=b:153677727
TEST=mandolin

Change-Id: I2956dcaad87cc1466deeca703748de33390b7603
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42219
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16 19:14:05 +00:00
Piotr Kleinschmidt 49e0e00168 mb/pcengines/apu2/mainboard.c: unify hexadecimal notation using capital letters
mainboard_intr_data table mixed hexadecimal notation with
both small and capital letters. Now, it is unified to capitals only.

Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com>
Change-Id: Icd8cf4324e72e87e7e98869872785523fb4e1809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42388
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16 14:37:19 +00:00
Kyösti Mälkki 7e75f33de5 sb/intel/common/pmutil: Add dump_all_status()
Change-Id: I10582941afd68425603f6c4cadd228797cd098e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16 10:19:35 +00:00
Kyösti Mälkki f71f3ae9c2 lib/malloc: Drop <cpu/x86/smm.h> include
Change-Id: I39b8dc37219195e88ea6396aa7e987e5e244bbab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-16 08:09:13 +00:00
Elyes HAOUAS da7749c5d6 soc/amd/picasso/include/soc/memmap.c: Add missing <stdint.h>
include <stdint.h> for 'uint32_t'.

Change-Id: I8768b7f0692ed703a060dc0406b517dc001cc25d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-16 08:06:35 +00:00
Kyösti Mälkki eadd251bf7 cpu/x86: Define MTRR_CAP_PRMRR
Followups will remove remaining cases of PRMRR_SUPPORTED and
SMRR_SUPPORTED in the tree.

Change-Id: I7f8c7d98f5e83a45cc0787c245cdcaf8fab176d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16 08:05:16 +00:00
Kyösti Mälkki 96cb2522fd sb/intel/i82801dx: Drop smm_setup_structures()
The only board that builds this does not have ACPI S3 support.
Also the code is wrong.

Change-Id: Ifb8e0ae5b6d862fa6a52b8e08197a84e7da4be36
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16 08:05:02 +00:00
Kyösti Mälkki 87e6796a90 soc/amd: Replace enable_smi_generation()
Change-Id: I9846df34fd2b6b15549fa33d3eda137544fa4219
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16 08:04:48 +00:00
Kyösti Mälkki b264c5ce10 sb/amd/x/hudson: Replace hudson_enable_smi_generation()
Change-Id: I08b2d1af16c247e66bf1a352887b0f9387055225
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16 08:04:27 +00:00
Kyösti Mälkki 0778c86b3b sb,soc/intel: Replace smm_southbridge_enable_smi()
Change-Id: I8a2e8b0c104d9e08f07aeb6a2c32106480ace3e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16 08:04:09 +00:00
Kyösti Mälkki 040c531158 soc/intel/common: Replace smm_soutbridge_enable(SMI_FLAGS)
Change-Id: I8c4dc5ab91891de9737189bd7ae86df18d86f758
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16 08:03:44 +00:00
Kyösti Mälkki 21ba5eea89 arch/x86: Declare global_smi_enable()
The call made at mp_ops.post_mp_init() generally
uses four different names. Unify these with followups.

  smm_southbridge_enable(SMI_EVENTS)
  smm_southbridge_enable_smi()
  hudson_enable_smi_generation()
  enable_smi_generation()

Furthermore, some platforms do not enable power button
SMI early. It may be preferred to delay the enablement,
but fow now provide global_smi_enable_no_pwrbtn() too.

Change-Id: I6a28883ff9c563289b0e8199cd2ceb9acd6bacda
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-16 08:03:27 +00:00
Kyösti Mälkki ad882c3b17 sb/intel: Remove spurious HAVE_SMI_HANDLER test
There are no side-effects in calling acpi_is_wakeup_s3()
and apm_control() is a no-op with HAVE_SMI_HANDLER=n.

Change-Id: Ia9195781955cc5fa96d0690aa7735fc590e527e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41986
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16 08:02:54 +00:00
Kyösti Mälkki b6585481e8 arch/x86: Create helper for APM_CNT SMI triggers
Attempts to write to APM_CNT IO port should always be guarded
with a test to verify SMI handler has been installed.

Immediate followup removes redundant HAVE_SMI_HANDLER tests.

Change-Id: If3fb0f1a8b32076f1d9f3fea9f817dd4b093ad98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41971
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-16 08:02:18 +00:00
Kyösti Mälkki 9446447475 sb/intel: Clean up some SMI enables
Change-Id: I191ad709fd3c6f906cd34b0053eeaebdb80d410d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-16 08:01:55 +00:00
Angel Pons f3973bd4cf i945 boards: Factor out MAX_CPUS
At least one mobile 945 series northbridge supports 4 threads, because
the dual-core Atom 330 CPU supports Hyper-threading. Therefore, we use
that as the default for this chipset.

Change-Id: I899ed1644d9b2da4fc72f09233a421200770110d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41845
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 22:56:48 +00:00
Angel Pons f6846efd84 gm45 boards: Factor out MAX_CPUS
The gm45 northbridge supports at most 4 threads. However, the only two
mobile Core 2 Quad models are not BGA956, so account for that as well.

Change-Id: Ie198ac4c366ec0bd53ddb337b6f9c03c331c73f5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-15 22:55:54 +00:00
Angel Pons babffce0eb pineview boards: Factor out MAX_CPUS
Pineview has at most 4 threads.

Change-Id: I0f45f002d0bab0345bc061ac3c7a29237a536cc5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41843
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 22:51:35 +00:00
Angel Pons 0f11e03220 haswell boards: Factor out MAX_CPUS
ULT only has 4 threads, but we are not changing it here to preserve
binary reproducibility.

Change-Id: I041c5dff2de514244f9c919c4c475cca979c34ce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41842
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 22:51:11 +00:00
Angel Pons a1dfce1ce0 x4x boards: Factor out MAX_CPUS
LGA775 CPUs can have at most 4 threads, and Eaglelake supports them.
As this socket is also used by other chipsets, temporarily place this
symbol into the northbridge scope until all chipsets are factored out.

Change-Id: I6e01363d995e135815cc70779e0cd5baf806cf60
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-06-15 22:50:39 +00:00
Angel Pons e5a7a1f314 arrandale boards: Factor out MAX_CPUS
Arrandale CPUs have at most 4 threads.

Change-Id: Ifecbf5583011ff5e36c576d582a6276bc9b72803
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41840
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 22:49:59 +00:00
Angel Pons d71754d1b9 sandybridge boards: Factor out MAX_CPUS
Also update autoport accordingly.

Change-Id: I12481363cf0e7afc54e2e339504f70632e8d72e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41839
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 22:49:23 +00:00
Martin Roth a202aec5fd include: update cbmem_possibly_online for vboot_before_bootblock
cbmem is not online when vboot runs before the bootblock. Update the
macro to reflect that.

BUG=b:158124527
TEST=Build & boot psp_verstage on trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I6fb4ad04f276f2358ab9d4d210fdc7a34a93a5bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-15 22:48:06 +00:00
Martin Roth cbf6e6bdba Makefile.inc: Remove all-y with CONFIG_ARCH_xx guards
The assumption up to this point was that if the system had an x86
processor, verstage would be running on the x86 processor.  With running
verstage on the PSP, that assumption no longer holds true, so exclude
pieces of code that cause problems for verstage on the PSP.

As a generalization, remove all-y for CONFIG_ARCH_xx guarded
makefiles.

BUG=b:158124527
TEST=Build and boot on Trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ia7dcfed699ee1c0cd5a5250431c5f05bf6d8b9c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-15 22:47:40 +00:00
Martin Roth 6b303d54aa vc/amd/fsp/picasso: Add AMD code to support psp_verstage
Add the AMD supplied code (modified to work with GCC) to the vendorcode
directory.  Verstage will be running on the PSP as a userspace
application under the bootloader, which is what bl_uapp signifies.

AMD is still working on documentation for the entire PSP userspace
application interface.

BUG=b:158124527
TEST=Build & boot psp_verstage on Trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie740c89afe2277eff279fc5c94f88ffd43a78a37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-15 22:20:13 +00:00
Martin Roth 4883252912 soc/amd/common/block/acpimmio: Update acpimmio for psp_verstage
Because the PSP maps the MMIO addresses that are used to non-
deterministic addresses, the accesses need to be able to find
the address at runtime.

BUG=b:158124527
TEST=Build & boot with Trembyle

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I68305e0f31956c57bfdee42025bdfe938703e82d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42061
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 22:10:16 +00:00
Martin Roth baba3e9610 console: Update for vboot before bootblock
Exclude pieces of console code from the vboot if running before
bootlock.  The PSP verstage code will re-implement some of
these in its own code.

BUG=b:123887623
TEST=Build with following patches

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ifc9fb0810e0816fe0a68e52287eda6145043a619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41815
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 22:07:12 +00:00
Martin Roth b9c2ecffda include/rules.h: Add vboot_before_bootblock to ENV_ROMSTAGE_OR_BEFORE
BUG=b:158124527
TEST=Build & boot Trembyle with PSP verstage

Change-Id: I3f5cc4d396c678f1020409cbdcb5127b2e0e6d89
Signed-off-by: Martin Roth <martin@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42379
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-15 22:03:11 +00:00