Commit Graph

35227 Commits

Author SHA1 Message Date
Martin Roth 8a3a3c820b security/vboot: Add option to run verstage before bootblock
For AMD's family 17h, verstage can run as a userspace app in the PSP
before the X86 is released. The flags for this have been made generic
to support any other future systems that might run verstage before
the main processor starts.

Although an attempt has been made to make things somewhat generic,
since this is the first and currently only chip to support verstage
before bootblock, there are a number of options which might ultimately
be needed which have currently been left out for simplicity.  Examples
of this are:
- PCI is not currently supported - this is currently just a given
instead of making a separate Kconfig option for it.
- The PSP uses an ARM v7 processor, so that's the only processor that
is getting updated for the verstage-before-bootblock option.

BUG=b:158124527
TEST=Build with following patches

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I4849777cb7ba9f90fe8428b82c21884d1e662b96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-15 21:04:00 +00:00
Kyösti Mälkki 61ba7fb2d9 cpu/intel: Remove obsolete comment in CAR setup
A looong time ago when cache_as_ram.S was built into romstage,
the stage was also linked twice. First at a fixed low address
and then again relocated at the final execute-in-place address.

Change-Id: Ic624feef6794f2c24e38459a45583d84fc07a484
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-15 19:14:13 +00:00
Kyösti Mälkki 44ef38f703 arch/x86: Remove NO_FIXED_XIP_ROM_SIZE
The variable SETUP_XIP_CACHE provides us a working
alternative.

Change-Id: I6e3befedbbc7967b71409640dc81a0c2a9b3e511
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41821
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-15 18:35:52 +00:00
Kyösti Mälkki 49c44cdccb arch/x86: Remove XIP_ROM_SIZE
When adding XIP stages on x86, the -P parameter was used to
pass a page size that covers the entire file to add. The same
can now be achieved with --pow2page and we no longer need to
define a static Konfig for the purpose.

TEST: Build asus/p2b and lenovo/x60 with "--pow2page -v -v" and
inspect the generated make.log files. The effective pagesize is
reduced from 64kB to 16kB for asus/p2b giving more freedom
for the stage placement inside CBFS. Pagesize remained at 64kB
for lenovo/x60.

Change-Id: I5891fa2c2bb2d44077f745619162b143d083a6d1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-15 18:34:45 +00:00
Kyösti Mälkki c36469e0b1 util/cbfstool: Add option --pow2page
For add-stage command, --pow2page is equivalent of passing
-P log2ceil(sizeof stage). The sizeof stage can be hard to
determine in Makefile to be passed on the commandline.

Change-Id: If4b5329c1df5afe49d27ab10220095d747024ad6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-06-15 18:34:27 +00:00
Felix Held 4824d747fc 3rdparty/amd_blobs: advance submodule pointer
This pulls in a newer version of the PSP-related blobs.

Change-Id: I6ff39260e9697512f78eb68435bd17ea83af35d5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-15 00:04:04 +00:00
Martin Roth 86ba0d73f3 soc/amd/picasso/graphics: implement map_oprom_vendev_rev
Picasso, Dali, and Pollock iGPU share the same PCI device ID, but need
different video BIOSes. This checks the vendor & device IDs along with
the revision and selects the correct video BIOS to use.

Also add the second VGA BIOS for Raven2-based SoCs and change all VGA
BIOS IDs to the format including the revision number.

Since SeaBIOS still expects the CBFS file name without the revision ID,
it won't find the VBIOS any more. As a temporary workaround add the
VBIOS for the silicon it will run on as VGA_BIOS_DGPU_*.

Change-Id: I8f48ecc3fbffddd21d1f830fbee26a09ac351e1c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/2040455
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14 19:08:08 +00:00
Subrata Banik 33d9c4ad7e drivers/intel/fsp2_0: Add FSP 2.2 specific support
• Based on FSP EAS v2.1 – Backward compatibility is retained.
• Add multi-phase silicon initialization to increase the modularity of the
FspSiliconInit() API.
• Add FspMultiPhaseSiInit() API
• FSP_INFO_HEADER changes
   o Added FspMultiPhaseSiInitEntryOffset
• Add FSPS_ARCH_UPD
   o Added EnableMultiPhaseSiliconInit, bootloaders designed for
     FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and
     continue to use FspSiliconInit() without change.

FSP 2.2 Specification:
https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html

Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41728
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14 17:48:31 +00:00
Duncan Laurie f7841d03e2 mb/google/volteer: Disable HDA PCI device when AUDIO=NONE
If there is no installed audio daughter board on volteer then the
HDA driver in the kernel will crash on resume.  In order to prevent
this disable the PCI device when AUDIO=NONE probe match is true.

BUG=b:147462631
TEST=boot on volteer and ensure that the PCI device at 0:1f.3 is gone

Change-Id: I4a436e1b76418030bf635427e490b54a713fdd33
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14 17:48:06 +00:00
Furquan Shaikh 76f1713ff2 mb/google/zork: Drop OEM_BIN configs
Zork family does not use OEM binary and so this change drops the
configs required for adding this binary.

Change-Id: Id38c67030e4055ab16934d1a900ee1cea5843b54
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14 16:55:55 +00:00
Furquan Shaikh b5d98667c6 mb/google/zork: Enable ELOG options
This change enables following ELOG options for zork family:
ELOG
ELOG_BOOT_COUNT
ELOG_GSMI
ELOG_BOOT_COUNT_CMOS_OFFSET

BUG=b:158875638
TEST=Verified that kernel reports GSMI loading correctly:
[    5.308982] gsmi version 1.0 loaded

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4f34a814e744e863f1fbfc19e37209cb7febbdcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14 16:55:44 +00:00
Alexey Buyanov 2232e89065 southbridge/intel/common: Introduce ASL2.0 syntax
Modify southbridge/intel/common .asl files to comply with ASL2.0 syntax for
better code readability and clarity

BUG=none
BRANCH=none
TEST= Google Parrot platform coreboot binary remains the same after the changes are applied

Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com>
Change-Id: Ia11769d5ac6154ed79d967d7bab36e12a1db751a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42084
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14 16:55:02 +00:00
Raul E Rangel 5591b91b1a soc/amd/picasso/aoac: Add wait_for_aoac_enabled
This way drivers can wait for their devices to be enabled.

I also rewrote enable_aoac_devices to take advantage of
wait_for_aoac_enabled.

BUG=b:153001807
TEST=Trembyle builds

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8e653c857e164f90439e0028e08aa9608d4eca94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14 16:53:44 +00:00
Raul E Rangel c64755bcd7 soc/amd/picasso/aoac: Set the Target Device State when powering on
If the OS sets the target device state to D3, we need to clear it so we
can reestablish register access.

BUG=b:153001807
TEST=Boot trembyle with I2C powered off and see it power back on.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If9bd1b7cfa7b8d074226c4dcdefc1a44cad8b940
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14 16:53:31 +00:00
Raul E Rangel d53c281d0b soc/amd/picasso: Move aoac functions to new file
This functionality is needed in the PSP and I can't include all of
southbridge.c.

BUG=b:153001807
TEST=Made sure trembyle still compiles

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3a38c655588d7836e1bd033e958a505774de871e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42324
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14 16:53:20 +00:00
Raul E Rangel 4f5936b456 soc/amd/picasso: Explicitly disable legacy UART
The legacy UARTs are supposed to default to off according to the
documentation (PPR for AMD Family 17h Model 18h). But legacy UART Range_0
is enabled after reset. The PSP might be enabling it or the documentation
might be wrong.

Having it enabled causes problems though. We have ACPI nodes defining
MMIO UARTs, and the kernel also probes for legacy UARTs. This results in
two drivers accessing the same device, one via MMIO and one via IO. I
suspect this was the cause of the garbage serial output.

Before the change you would see the following in the console:
[    0.741108] serial8250: ttyS3 at I/O 0x2e8 (irq = 3, base_baud = 115200) is a 16550A

After this change, we no longer see it.

BUG=b:152079780, b:157858890
TEST=Boot trembyle and make sure serial is still working.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9d837e449b961dbb55d1301d2107838e26b3f892
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-06-14 16:52:58 +00:00
Kyösti Mälkki 5d0893adce console, PCI: Remove EARLY_PCI_BRIDGE support in verstage
The purpose of pci_early_bridge_init() is to temporarily configure
PCIe rootport (or PCI bridge) on bus 0 to configure PCI device BARs
on the secondary bus. Currently used and tested only with UART_OXPCIE.

Since those BARs do not reset on stage changes, it is not necessary
to redo those steps for verstage or postcar. Note that the option
does not really work with many of the later platforms where PCIe
pins/links/lanes are configured late in FSP-M or similar blob.

Change-Id: I148f44c76c61edcfd8ab1c8c531cd2e6ca343130
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14 16:52:48 +00:00
David Wu 83ca56acdf mb/google/volteer/var/terrador: Update dq/dqs mappings
Update dq/dqs mappings based on terrador schematics.

BUG=b:156435028,b:151978872
BRANCH=none
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I97697a3dd9b88eaffe6e2b1be7bd346979cbc956
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-06-14 16:51:47 +00:00
Jonathan Zhang 7454005a4f soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGS
FSP_NV_STORAGE HOB is supported in CPX-SP FSP ww22 release.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Ida06fa7f7c7937f4e66a83fdecbca8bc208d626f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42024
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14 16:51:10 +00:00
Aaron Durbin 4a3a73c042 soc/amd/picasso: correct MCFG ACPI table
The start and end bus number in the MCFG ACPI table is inclusive.
Therefore, the number of buses decoded needs to be subtracted by
1.

BUG=b:158874061

Change-Id: Ic773bc1e0ccaa99af45d1a53919f6480887fa37e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42329
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14 16:51:01 +00:00
Deepika Punyamurtula 1e53a89f63 mb/google/volteer: Enable thermal sensor 4 in DPTF for volteer
Enables the fourth thermal sensor for fan in DPTF for volteer

BRANCH=None
BUG=b:149722146
TEST= On volteer system check
`cat /sys/class/thermal/thermal_zone5/type` for TSR3

Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com>
Change-Id: Ie11496828133aa71f1017f759516e2e5d3dff2d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-06-14 16:50:43 +00:00
Tim Wawrzynczak 103bd5e4bb dptf: Introduce new paradigm for configuring DPTF parameters
Currently, configuring and reviewing DPTF parameters is difficult
because DPTF tables and methods are defined in static ASL files, and are
littered with #ifdefs which both define parameters and influence
behavior (e.g., whether a method is included or not). This patch train
is an effort to bring DPTF support to our ACPI DSDT/SSDT generation
framework.

This first patch is very minimal, and includes only creation of the
DPTF device (in the DSDT).

BUG=b:143539650
TEST=compiles (later tests get more comprehensive).

Change-Id: I14df9f422c911677aeea25552ac1822a9462c58a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41883
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14 16:48:55 +00:00
Alex Levin f3668fc1de soc/intel/tigerlake: enable CPU_INTEL_COMMON
Since we plan to use VMX, enable CPU_INTEL_COMMON.

BUG=b:157388365
TEST=tested on Volteer

Signed-off-by: Alex Levin <levinale@chromium.org>
Change-Id: I5e7bdb4310947dd8a94ee554834a67ce94377ea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-06-14 16:48:25 +00:00
Marshall Dawson 3e2fabfa5e soc/amd/picasso: Increase SMM_RESERVED_SIZE
Correct a message of "Error: Can't add stage_cache 57a9e101 to imd".
ramstage is 0xffc90 and adding FSP-S (0x50000) failed.  Increase the
reserved region of SMRAM to accommodate both images.

BUG=b:158704095
TEST=Boot Mandolin and check console log

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I51595d80d4779e995ec2a26e395cf95d666a309e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42314
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14 16:48:12 +00:00
Shiyu Sun c8fa51b877 mb/google/puff: add MST and LSPCON details to devicetree
Added device hid info to the MST and LSPCON devices.

BRANCH=None
BUG=b:156546414
TEST=Manual tested and able to see update on sysfs and ssdt table

Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Change-Id: Iaef6c08f241ea671d1487a8524162dbb438b8e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-06-14 16:47:41 +00:00
Paul Menzel bc0fc39022 soc/intel/cannonlake/acpi: Capitalize hex number to unify with Skylake
diff -ur src/soc/intel/skylake/acpi/pch_hda.asl src/soc/intel/cannonlake/acpi/pch_hda.asl
    --- src/soc/intel/skylake/acpi/pch_hda.asl      2020-05-12 11:17:42.780293920 +0200
    +++ src/soc/intel/cannonlake/acpi/pch_hda.asl   2020-05-12 11:17:42.756294169 +0200
    @@ -4,7 +4,7 @@

     Device (HDAS)
     {
    -       Name (_ADR, 0x001F0003)
    +       Name (_ADR, 0x001f0003)
            Name (_DDN, "Audio Controller")
            Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553"))

Change-Id: Ic8b874163ddede72a75e0dc94021683bca3e7859
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-06-14 16:47:11 +00:00
Jonathan Zhang 3a6d8fd889 soc/intel/xeon_sp/cpx: configure FSP-M UPD parameters
Configure FSP-M UPD parameters.

TESTED=Boot CPX-SP based server.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I2d0762a742d8803c7396034e3244120c1e8ece67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14 16:46:15 +00:00
Jonathan Zhang c110595503 soc/intel/xeon_sp/cpx: add cpu entries in ssdt
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I4d057a7c385ca563bfcc7ad44f651ad1f8ca003c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14 16:45:55 +00:00
Jonathan Zhang 890cf2299d soc/intel/xeon_sp/cpx: fix MADT ACPI table
Fix MADT table generation to keep IIO stack design in consideration.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: If1bf6e39db545e227e9867aa8d24f7db1d820216
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14 16:45:24 +00:00
Jonathan Zhang 110d1a98e1 soc/intel/xeon_sp/cpx: add IIO stack resources to DSDT
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: Iec89551a8b88a683db5857e3a6ab4af5e446cb5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14 16:45:10 +00:00
Jonathan Zhang 3172f987fa soc/intel/xeon_sp/cpx: add NUMA ACPI tables
Add NUMA ACPI tables: SRAT, SLIT.

TESTED=Boot CPX-SP based server, check /sys/firmware/acpi/tables
for SRAT/SLIT tables.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I3374b802afd2d001e841afd85e7ae07bc27c01ff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-06-14 16:44:58 +00:00
Paul Menzel 2c4866228e util/board_status: Also check remotely retrieved coreboot console log
Currently, the logs are only checked, if retrieved locally. Moving it
after the if statement, now logs retrieved remotely are also checked.

The change in behavior is, that now all commands are executed first, so
before hitting this error, other errors might occur unrelated to the
console log.

Change-Id: I016bbde66c58a654042ad880c6007ddc1d143691
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-14 16:44:05 +00:00
Tim Chen 5b185840f7 mb/google/hatch/vr/puff: Set up PL2 and PsysPL2
This patch adds correct PL2 baseline setting and PsysPL2 for different
SKUs. There is no way to identify the barral jack power rating, the
assumption is following that ships with the product:
1. i3/i5/i7: 90W BJ
2. Celeron/Pentium: 65W BJ

For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the
original settings as 90% of adapter rating for PsyspL2/PL4 and PL2
as min(PL2, 0.9n) where n is adapter rating power.

BUG=b:143246320
TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct

Change-Id: Ib16d4f65707801b430f06892ab45ecfa7551593f
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-06-14 16:43:47 +00:00
Jeff Chase ad1a835c69 mb/google/fizz: add variant chipset display init
The Endeavour variant does not have a DisplayPort input so there's no
need to wait for it.

BUG=b:147830399
BRANCH=none
TEST=boot endeavour; check coreboot logs

Signed-off-by: Jeff Chase <jnchase@google.com>
Change-Id: I30c7c47f19a61ce66c6c923864d80870d2761859
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2020-06-14 16:43:05 +00:00
Matt DeVillier 3380faa283 util/intelmetool: Add support for Intel Cannon Point LP HECI Controller
Tested on Intel NUC 8i5BEH (CFL) and Purism Librem Mini (WHL)

Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I1054455fff2dcae8d17afe2adf3329eb44aa862a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-14 16:42:47 +00:00
Meera Ravindranath 17c6bf7a24 mb/google/dedede: Enable early EC software sync
BUG=none
BRANCH=none
TEST=Verify sysjump from EC console, EC sync in romstage in AP
     console and crossystem reflect ecfw_act as RW

Change-Id: Ief96fe481c94acef3754881cf1f453699fbfa52e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41396
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14 16:42:20 +00:00
Meera Ravindranath d6f7ecb12f mb/google/dedede: Select Recovery Cache Kconfig option
BUG=none
BRANCH=none
TEST=Boot WaddleDoo in recovery and populate the recovery MRC cache.
     The subsequent recovery boot should boot out of the stored
     recovery MRC cache and skip memory training.

Change-Id: Ief86fe481c94abef3754881cf1f454699fbfa52e
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41162
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14 16:42:06 +00:00
Kyösti Mälkki ba5a951a93 sb/intel/i82801ix: Fix SPDX license header
Change-Id: I4c8ef49f86f6d5344741ab92035e108cccfe30b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-14 14:09:34 +00:00
Edward O'Callaghan 0490f5affb mb/google/hatch: Switch USB2 port1 and port3 on Noibat
Switch USB2 port1 and port3 for noibat due to circuit change.

BUG=b:154585046,b:156429564
BRANCH=none
TEST=none

Change-Id: I711038624f3efe397be73c29a940b3e17802598f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42296
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-14 03:43:44 +00:00
Furquan Shaikh ad78553f5d soc/amd/picasso/acpi: Add a wrapper method WAL1 for calling ALIB function 1
ALIB function 1 needs to be called every time there is a change in
AC/DC state of the system. This change adds a wrapper method that can
be called by PNOT (method to notify system power state change) to
report to ALIB that system power state has changed i.e. AC <-> DC.

Additionally, this change drops the call to ALIB from _INI method
since the PWRS object might not be initialized correctly at that
point. Instead EC makes a call to PNOT when PWRS is initialized.

This wrapper also fixes the value of power state being passed into
ALIB. ALIB expects 0 = AC and 1 = DC. On the other hand, PWRS reports
1 as AC and 0 as DC. WAL1() takes care of inverting the PWRS state
before passing into ALIB.

BUG=b:157752693
TEST=Verified that WAL1() gets called on AC connect/disconnect.

Steps followed:
$ echo 1 > /sys/module/acpi/parameters/aml_debug_output
$ dmesg -w | grep ACPI
[   76.306947] ACPI Debug:  "EC: AC DISCONNECTED"
[   76.307064] ACPI Debug:  "ALIB call: func 1 params 0x03 0x00 0x01"
[   82.264946] ACPI Debug:  "EC: GOT PD EVENT"
[   82.539833] ACPI Debug:  "EC: GOT PD EVENT"
[   82.753721] ACPI Debug:  "EC: GOT PD EVENT"
[   82.843676] ACPI Debug:  "EC: GOT PD EVENT"
[   82.970596] ACPI Debug:  "EC: AC CONNECTED"
[   82.970659] ACPI Debug:  "ALIB call: func 1 params 0x03 0x00 0x00"
[   83.047598] ACPI Debug:  "EC: GOT PD EVENT"
[   84.804733] ACPI Debug:  "EC: GOT PD EVENT"
[   86.317934] ACPI Debug:  "EC: GOT PD EVENT"
[   86.385920] ACPI Debug:  "EC: GOT PD EVENT"
[   86.515830] ACPI Debug:  "EC: AC DISCONNECTED"
[   86.515922] ACPI Debug:  "ALIB call: func 1 params 0x03 0x00 0x01"
[   90.089062] ACPI Debug:  "EC: GOT PD EVENT"
[   90.357914] ACPI Debug:  "EC: GOT PD EVENT"
[   90.573812] ACPI Debug:  "EC: GOT PD EVENT"
[   90.662744] ACPI Debug:  "EC: GOT PD EVENT"
[   90.788706] ACPI Debug:  "EC: AC CONNECTED"
[   90.788835] ACPI Debug:  "ALIB call: func 1 params 0x03 0x00 0x00"
[   90.865675] ACPI Debug:  "EC: GOT PD EVENT"
[   92.621793] ACPI Debug:  "EC: GOT PD EVENT"

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I1f2ade28ca35378ebf4647d8df3d2ea4d0b08096
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14 00:47:15 +00:00
Furquan Shaikh 80c555d7a8 ec/google/chromeec: Call \PNOT () on initializing AC power state
This change calls \PNOT () method when AC power state is initialized
to allow platform code to take appropriate action.

BUG=b:157752693

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I089e9096f78728ddc5df2d8cb8f22f65b30b02dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-14 00:47:03 +00:00
Kyösti Mälkki dc6bb6cb82 cpu/intel/car: Use symbols for CAR MTRR setup
Change-Id: I32d7337ccf8005c7fb65d2efea40c122093d4dd9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-06-13 12:26:34 +00:00
Kyösti Mälkki ed318f2001 arch/x86: Add symbols for CAR MTRRs in linker script
This allows to remove references to CONFIG_DCACHE_RAM entries in
most cache_as_ram.S files. While Kconfig variable names appear
for every stage, linker symbol names will only appear in stages
they are valid in.

Also, linker scripts have LOG2CEIL which comes in handy to enforce
MTRR alignments.

Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30872
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13 12:25:18 +00:00
Alexey Buyanov 03248033e7 soc/intel/common: Introduce ASL2.0 syntax
Modify soc/intel/common .asl files to comply with ASL2.0 syntax for
better code readability and clarity

BUG=none
BRANCH=none
TEST= Deltan coreboot binary remains the same after the changes are applied

Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com>
Change-Id: I8f95cf88f499d9f9bdd8c80c95af52f8fd886cdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-06-13 09:03:32 +00:00
Furquan Shaikh e334fea94b arch/x86: Include id.ld unconditionally in memlayout.ld
Now that Picasso uses its own memlayout.ld, always include id.ld in
arch/x86/memlayout.ld.

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I04b59c2a273cad0a2e64dbc325c0b09fca254558
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42266
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-06-13 06:51:18 +00:00
Furquan Shaikh 31be15c7a2 arch/x86: Drop early_ram.ld
Now that Picasso uses its own linker script, early_ram.ld from
arch/x86 is unused and hence is dropped as part of this change.

BUG=b:155322763

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ida83d40d005ddab789628a1581389fc487b10d4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-13 06:51:07 +00:00
Furquan Shaikh bc45650b5f soc/amd/picasso: Place early stages and data buffers at the bottom of DRAM
This change updates memlayout.ld for Picasso to place all early
stages (bootblock, romstage, FSP-M, verstage) and data buffers (vboot
workbuf, APOB, preram-cbmem console, timestamp, early BSP stack) at
the bottom of DRAM starting at 32MiB. This uses static allocation for
most components by defining Kconfig variables for base and size. It
relies on the linker to complain if any of the assumptions are broken.

This also allows romstage to use linker symbols for
_early_reserved_dram and _eearly_reserved_dram to store information in
CBMEM about the early DRAM usage by coreboot before ramstage starts
execution. This allows ramstage to reserve this memory region in BIOS
tables so that S3 resume can reuse the same space without corrupting
OS memory.

BUG=b:155322763
TEST=Verified memory reported by coreboot:
Writing coreboot table at 0xcc656000
 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
 1. 0000000000001000-000000000009ffff: RAM
 2. 00000000000a0000-00000000000fffff: RESERVED
 3. 0000000000100000-0000000001ffffff: RAM
 4. 0000000002000000-000000000223ffff: RESERVED
 5. 0000000002240000-00000000cc512fff: RAM
 6. 00000000cc513000-00000000cc6bffff: CONFIGURATION TABLES
 7. 00000000cc6c0000-00000000cc7c7fff: RAMSTAGE
 8. 00000000cc7c8000-00000000cd7fffff: CONFIGURATION TABLES
 9. 00000000cd800000-00000000cfffffff: RESERVED
10. 00000000f8000000-00000000fbffffff: RESERVED
11. 0000000100000000-000000042f33ffff: RAM
12. 000000042f340000-000000042fffffff: RESERVED

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I009e1ea71b5b5a8e65eba16911897b2586ccfdb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-06-13 06:50:51 +00:00
Furquan Shaikh c3bb6923bd util/cbfstool: Drop IS_TOP_ALIGNED_ADDRESS() check in cbfstool_convert_fsp
This change drops the check for IS_TOP_ALIGNED_ADDRESS() before
setting offset to 0 in cbfstool_convert_fsp(). If the user provides a
baseaddress to relocate the FSP to, then the offset should be set to 0
since there is no requirement on where the file ends up in cbfs. This
allows the user to relocate the FSP to an address in lower DRAM.

BUG=b:155322763

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ibeadbf06881f7659b2ac7d62d2152636c853fb9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-13 06:49:50 +00:00
Furquan Shaikh 00a8ed8fcd cbmem_id: Add CBMEM ID for early DRAM usage
This change adds a new CBMEM ID (CBMEM_ID_CB_EARLY_DRAM) that can be
used by platform code to stash details of early DRAM used by
coreboot.

BUG=b:155322763

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I913c744fdce2f9c36afdc127b2668fccf57dde58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-13 06:49:42 +00:00
Furquan Shaikh 3b03206426 soc/amd/picasso: Add custom memlayout.ld file
This change copies src/arch/x86/memlayout.ld file to
src/soc/amd/picasso/ and sets MEMLAYOUT_LD_FILE config variable to
point to this newly added file. Unused elements from the memlayout.ld
file are dropped and path to early_dram.ld is updated to include the
one from src/arch/x86.

BUG=b:155322763

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I59bf5f93b712407ddcc9fb8a46167936c6c28a76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-06-13 06:49:30 +00:00