Add a missing period, use "SoC" with lowercase 'o' to refer to a "System
on a Chip", fix up the redundant "CRB board" expression (that stands for
"Customer Reference Board board"), switch the position of a verb and its
adverb ("never was" ---> "was never") to sound more natural, and replace
"depreciate" with "deprecate" for semantic correctness.
Change-Id: Ic821a9030d4ff32c76765f51f1feb0f5503d4cc0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68330
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The release of coreboot 4.18 is delayed and thus version 4.19 won't be
released in upcoming November. Instead, just mention the version to be
more flexible about the date.
Change-Id: I33213479b02c2159beca78432aca775a04409e4c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68261
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SoC Intel Quark is unmaintained and various efforts to revive it
failed. Thus, deprecate the following components with the 4.18 release.
* Intel Quark SoC
* Intel Galileo mainboard
The support for these components will be dropped with the release 4.20.
Change-Id: I738ad74da043649107473dc0c2e6adf343e4cd35
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68260
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When system_uuid CBFS file is present and contains the UUID
in a string format, the driver will parse it and convert to binary
format to populate the SMBIOS type 1 UUID field.
TEST=Add UUID file and boot MSI PRO Z690-A DDR4 WIFI and check with
dmidecode if the UUID is populated correctly.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I22f22f4e8742716283d2fcaba4894c06cef3a4bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64639
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some mainboards have a header connected to the SPI bus, which can be
used to connect a second flash chip and override the onboard flash. This
allows one to boot coreboot on the system without ever having to flash
the onboard flash. HP boards with this header all seem to use the same
2x8 or 2x10 header layout, so document the pinout.
Change-Id: Ic2bf1244adfb78872340f212519c6ab33e26646a
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67818
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A spelling mistake in the markdown reference to the coreboot vs EDK II
bootflow diagram was previously fixed, but the actual filename was not
changed resulting in a broken reference.
Change-Id: I512646e9af312ba2e1db8f597f6fffa8d54a3515
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67782
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This explains how to enable the SMBus console in coreboot
and its Kconfigs.
Change-Id: I50cafbbaaea133c9ea50131e455151287c96176a
Signed-off-by: Husni Faiz <ahamedhusni73@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
De-duplicate common initialization code (self-test and device
identification) and put it in a new ipmi_if.c unit, which is
supposed to work with any underlying IPMI interface.
Change-Id: Ia99da6fb63adb7bf556d3d6f7964b34831be8a2f
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Add a section explaining how the detect feature works and when it should
be used.
Change-Id: Ife5178d4565e76d0ff436c835c9c47525015c3ed
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Having multiple top-level headings breaks sphinx-doc's TOC generation,
so adjust driver sub-pages to only have a single one. Adjust other
headings as needed to preseve page layout.
Change-Id: Ib8a334c73daefffafa779957cc8e47a9cad4a202
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Move the devicetree driver example into a separate page under the
drivers category, and link to it from both the devicetree page and
the drivers index page. This makes more sense from a grouping
perspective and makes the info easier to find.
Change-Id: Ic3ca80b93a0020737c7ccb5313a0877172022e1a
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Recommonmark doesn't support markdown tables. Replace them with embedded
reStructuredText tables as described in the documentation guidelines.
Change-Id: I2d562603d5a6b6fe71e6729e9c44440af253ad20
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67668
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the Google Meet link to match the one found in the meeting
agenda and the reminders sent on the various community forums.
Change-Id: Ic4b8e0bb01e57850ea199c62b66a16e4d14de5c5
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Move devicetree.md from acpi/ to getting_started/. The devicetree has
nothing to do with ACPI and getting_started has the most similar
information about coreboot.
Change-Id: I873b293f036a9e3bcdc98135386f9158c645513c
Signed-off-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Part of the content was on the same line as the heading.
Change-Id: Ia19487d80e9f004d59f96ff09e1f3de4f37c2f77
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67000
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit feb551a92550fcc28b32aca77117aa743018b233.
Adding new variant "pazquel360" is not needed.
BUG=b:239599467
TEST=emerge-trogdor coreboot
Signed-off-by: chaogui@google.com
BRANCH=none
Change-Id: I4878d3a54f96fb9d38f2da1a1c918dfdef80a301
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66805
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board is no longer in the tree.
Change-Id: Ie4a626ce85fe0dc2b2d826dd8830a8e80ec331aa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
coreboot uses TianoCore interchangeably with EDK II, and whilst the
meaning is generally clear, it's not the payload it uses. EDK II is
commonly written as edk2.
coreboot builds edk2 directly from the edk2 repository. Whilst it
can build some components from edk2-platforms, the target is still
edk2.
[1] tianocore.org - "Welcome to TianoCore, the community supporting"
[2] tianocore.org - "EDK II is a modern, feature-rich, cross-platform
firmware development environment for the UEFI and UEFI Platform
Initialization (PI) specifications."
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4de125d92ae38ff8dfd0c4c06806c2d2921945ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65820
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
- Move configs for PCIe ports not present on z220_sff_workstation
from the devicetree.cb of base board to the overridetree.cb of
z220_cmt_workstation.
- Add a note for ME/AMT Flash Override jumper, for it is hard to
flash from OEM firmware either internally or externally without
closing this jumper.
- Add a side note for similar HP Compaq Elite 8300 SFF.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I35d8b97f52a83910a61c12b1f7367ee7a19a9ad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a new variant called Pazquel360 \
that is identical to Pazquel for now.
BUG=b:239987191
TEST=make
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I0a9ca4a59fb44256d0d8fcdbdf2a7db533c84412
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Bob Moragues <moragues@google.com>
Using 'convert' to convert the SVG logo to BMP for Tianocore
introduces terrible aliasing, so add a logo in BMP format
(converted using GIMP).
The default logo file used by Tianocore will be changed in a
subsequent commit.
Change-Id: I2490707a330713709dd4ba8ae99b22b123ba64da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Add the white hare coreboot logo in Documentation so that it can be
used for various things, including the bootsplash for edk2.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia3a1d64cc3bf695f88e163eda96e03b841ad04a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65931
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Link to Linux kernel coding style changed, fix it.
Change-Id: I9792d360d301b93c255306488c90375c6cc882c4
Signed-off-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Commits that fix a recently-introduced regression can be submitted early
to minimise the impact of said regression. However, it is important that
the commit message properly reflects what is being fixed and what commit
introduced the issue.
Change-Id: Ifd49582ae1cbcfe6ee3816e0658dbd0432801161
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63780
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Markdown, definition file and sconfig source codes don't need to be
executables. This patch fixes that.
Signed-off-by: Petr Cvek <petrcvekcz@gmail.com>
Change-Id: Ic97d684318c689259f7895e3dfbd552434c3882e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This adds a style file for the markdown linter mdl.
The tool can be found on archive.org at the URL:
https://web.archive.org/web/20220407032312/https://github.com/markdownlint/markdownlint
This does 2 things:
- Sets that line length limit to 72 characters as requested in the docs
about writing the documentation.
- Excludes several rules that were added for a particular markdown
parser. My opinion is that these rules make the text versions of the
markdown harder to read.
To use this style file, run:
$ mdl -s Documentation/.mdl_style.rb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I98289492ae3e920d440f0e5c308a3590fb89d9fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8e0c96dc4b68e60f9a36afb361c4d1c6f9742c31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
A few of the brackets and bold text asterisks in the markdown links were
missing their corresponding closing symbol.
Change-Id: I9bfab1d2c83bdc12586bd31b1939bd241df2e932
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
The tutorial documents were updated from the wiki very early in the
transition to markdown, and the style has changed over time. This
updates the markdown style to match documents that are being created
now.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I619c04f420042f530335482c30070436f9190865
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
We have too many acronyms to keep track of. At one point, AMD and
Intel used to use the same terms for things, but no longer. When I
look at Intel patches now, I have no idea what they mean anymore.
When I started trying to do the release notes, I kept having to
look up the acronyms, so I figured I'd make a list.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4571bf468bbfc6a1a6f33399ba61032a18fe41ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Boards using VBOOT_VBNV_EC (nyan, daisy, veyron, peach_pit) are all
ChromeOS devices and they've reached the end of life since Feb 2022.
Therefore, remove VBOOT_VBNV_EC for them, each with different
replacement.
- nyan (nyan, nyan_big, nyan_blaze): Add RW_NVRAM to their FMAP (by
reducing the size of RW_VPD), and replace VBOOT_VBNV_EC with
VBOOT_VBNV_FLASH.
- veyron: Add RW_NVRAM to their FMAP (by reducing the size of
SHARED_DATA), and replace VBOOT_VBNV_EC with VBOOT_VBNV_FLASH. Also
enlarge the OVERLAP_VERSTAGE_ROMSTAGE section for rk3288 (by reducing
the size of PRERAM_CBMEM_CONSOLE), so that verstage won't exceed its
allotted size.
- daisy: Because BOOT_DEVICE_SPI_FLASH is not set, which is required for
VBOOT_VBNV_FLASH, disable MAINBOARD_HAS_CHROMEOS and VBOOT configs.
- peach_pit: As VBOOT is not set, simply remove the unused VBOOT_VBNV_EC
option.
Remove the VBOOT_VBNV_EC Kconfig option as well as related code, leaving
VBOOT_VBNV_FLASH and VBOOT_VBNV_CMOS as the only two backend options for
vboot nvdata (VBNV).
Also add a check in read_vbnv() and save_vbnv() for VBNV options.
BUG=b:178689388
TEST=util/abuild/abuild -t GOOGLE_NYAN -x -a
TEST=util/abuild/abuild -t GOOGLE_VEYRON_JAQ -x -a
TEST=util/abuild/abuild -t GOOGLE_DAISY -a
TEST=util/abuild/abuild -t GOOGLE_PEACH_PIT -a
BRANCH=none
Change-Id: Ic67d69e694cff3176dbee12d4c6311bc85295863
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
It’s a section title, so mark it up as a title as it’s done similarily
in other documents.
Change-Id: If9d524afe6f80ae1b2704d11617786ee923814b2
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The sentence about using SeaBIOS as secondary payload sounded
confusing, so reword it. While at it, improve and extend on SeaBIOS
features.
Change-Id: Ic06b9f56ab8082f2e6eff5fd8d31525429fd948d
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Now that the release has been tagged, update the release notes with the
final data and statistics.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If4c9d6befd82e9a134ee645e97111b4489adacc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
These are the final release notes before the release. They will be
updated immediately following the release with final numbers and
the commit ids that the release spans.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id9491ad9aa6ab3eb5504bee85591f3b1d9bf6cc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Add notes for significant changes to payloads, such as new payloads and
version updates.
Change-Id: I607d732beee07396a8002e5e504375d9dc4d7eda
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64752
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There shouldn't be any significant changes in meaning.
- Fix formatting issues
- Reword some text
Change-Id: I4e37605ef2371e6c4affbe6cb6c67e0875e89a1f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
The description.md file for the intelp2m utility wasn't the description
that was needed - just a subject, and what language it was written in.
It was instead a set of more full documentation, so move it into the
Documentation directory and create a new description file.
Change-Id: Ia180ae41f91f8b8eb408351a9e44e899edc031d3
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This fixes the following warnings:
mainboard/starlabs/common/flashing.md::
WARNING: image file not readable:
- mainboard/starlabs/common/fwupdVersion.png
- mainboard/starlabs/common/BiosLock.jpg
- mainboard/starlabs/common/SwitchBranch.png
cbfstool/index.md::
WARNING: document isn't included in any toctree
internals/devicetree_keywords.md::
WARNING: document isn't included in any toctree
mainboard/asus/wifigo_v1.md::
WARNING: document isn't included in any toctree
mainboard/google/index.md::
WARNING: document isn't included in any toctree
mainboard/starlabs/common/flashing.md::
WARNING: document isn't included in any toctree
releases/boards_supported_on_branches.md::
WARNING: document isn't included in any toctree
WARNING: None:any reference target not found:
- releases/coreboot-4.16-relnotes
- releases/coreboot-4.15-relnotes
- releases/coreboot-4.14-relnotes
- releases/coreboot-4.13-relnotes
- releases/coreboot-4.12-relnotes
- releases/coreboot-4.11-relnotes
- releases/coreboot-4.10-relnotes
- releases/coreboot-4.9-relnotes
- releases/coreboot-4.8.1-relnotes
- releases/coreboot-4.7-relnotes
- releases/coreboot-4.6-relnotes
- releases/coreboot-4.5-relnotes
- releases/coreboot-4.4-relnotes
- releases/coreboot-4.3-relnotes
- releases/coreboot-4.2-relnotes
- releases/coreboot-4.1-relnotes
- ../../src/soc/intel/common/block/cse/cse.c
Change-Id: I22273bc1bc34b6297cef4e594c454c2316d4215a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
In the last coreboot leadership meeting, the doxygen documentation was
declared to be dead. Remove it.
Doxygen style comments can still be added to files, and we may generate
doxygen based documentation, but it won't be for the entire project, but
instead just for those individual areas where it is being maintained.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8983a20793786a18d2331763660842fea836aa2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Also known as "SeaGRUB", running GRUB2 atop SeaBIOS proves to be a
useful configuration, since SeaBIOS has improved its hardware
compatibility. For example, some USB drive can work under SeaBIOS but
do not work under native GRUB2, and GRUB2 can use BIOS call (provided
by SeaBIOS) as a fallback method to access hardware if it is present.
But more option is added addition to "SeaGRUB": now GRUB2 and SeaBIOS
can be built as secondary payloads, and "SeaGRUB" is now implemented
as "Primary SeaBIOS + Secondary GRUB2 (selected) + config files".
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ie681fa231abfe4a8f1e4510b3c17957550a9d2f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This board never made it to production, and development on it has long
since stopped; it is a maintenance burden, therefore drop it from the
tree.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ieb12a95ff56c3437cb88df8ef3f6ae115ad53446
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This documents the boards that have been removed from the master branch,
and which branch to check out to build or work on them.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iee25db13e2c1b0b9131fd2032a26ece45aba4f42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This fixes the following issues found by the markdown lint tool, mdl:
MD014 Dollar signs used before commands without showing output
MD026 Trailing punctuation in header
MD030 Spaces after list markers
MD031 Fenced code blocks should be surrounded by blank lines
MD040 Fenced code blocks should have a language specified
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I82317f51c003b2c23d64c3cbbcecbf9a39d5d509
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This removes the need for a tool to generate simple identity pages.
Future patches will link this page table directly into the stages on
some platforms so having an assembly file makes a lot of sense.
This also optimizes the size of the page of each 4K page by placing
the PDPE_table below the PDE.
Change-Id: Ia1e31b701a2584268c85d327bf139953213899e3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The services page documents various services and tools which are
provided by the project. It's more related to the infrastructure and
less related to the community section.
Thus, move it to the infrastructure section.
Change-Id: I0ca2aba8ae817cf874367fa17e567065aec99a93
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
In preparation for CB:62442, rename the section for infrastructure
related things to "Project infrastructure & services".
Change-Id: I1ba8a2e2070a79d8c9e955133203f9bb9f58cb8e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Although we're looking at updating the build system, we don't have a
strict timeframe that this will happen. Until it does, we'll be using
the current Jenkins configuration.
This commit give some minor updates to the instructions and current
state of the builders.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ifa094a6d0450da4ab58e23d7b56e65e6101ee931
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Break TPM related Kconfig into the following dimensions:
TPM transport support:
config CRB_TPM
config I2C_TPM
config SPI_TPM
config MEMORY_MAPPED_TPM (new)
TPM brand, not defining any of these is valid, and result in "generic" support:
config TPM_ATMEL (new)
config TPM_GOOGLE (new)
config TPM_GOOGLE_CR50 (new, implies TPM_GOOGLE)
config TPM_GOOGLE_TI50 (new to be used later, implies TPM_GOOGLE)
What protocol the TPM chip supports:
config MAINBOARD_HAS_TPM1
config MAINBOARD_HAS_TPM2
What the user chooses to compile (restricted by the above):
config NO_TPM
config TPM1
config TPM2
The following Kconfigs will be replaced as indicated:
config TPM_CR50 -> TPM_GOOGLE
config MAINBOARD_HAS_CRB_TPM -> CRB_TPM
config MAINBOARD_HAS_I2C_TPM_ATMEL -> I2C_TPM && TPM_ATMEL
config MAINBOARD_HAS_I2C_TPM_CR50 -> I2C_TPM && TPM_GOOGLE
config MAINBOARD_HAS_I2C_TPM_GENERIC -> I2C_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_LPC_TPM -> MEMORY_MAPPED_TPM
config MAINBOARD_HAS_SPI_TPM -> SPI_TPM && !TPM_GOOGLE && !TPM_ATMEL
config MAINBOARD_HAS_SPI_TPM_CR50 -> SPI_TPM && TPM_GOOGLE
Signed-off-by: Jes B. Klinke <jbk@chromium.org>
Change-Id: I4656b2b90363b8dfd008dc281ad591862fe2cc9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch adds a section to the coding style that explicitly clarifies
the use of GCC extensions in coreboot (which has been long-standing
practice anyway), and expressly allows their use.
See the mailing list discussion for more details:
https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/3C2QWAZ5RJ6ME5KXMEOGB5GW62UTXCLS/
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0d0eb90d6729fefeb131cdd573ad51f1884afe11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This patch fixes the table issue in markdown file identified with commit
96481066 (Documentation: gpio: Update table as per coreboot guidelines).
BUG=b:211573253, b:211950520
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ifd8265b92b5ef0dcabb754371591477ca19c39be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The "Getting started" section is not an appropriate place for the
documentation license. It should rather be listed in the main menu.
Thus, move it there.
Change-Id: I8bfc4f52da8a93d78a62e3a68fd6f1dc8ae4d335
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This change mostly changes links that were identified as broken by
the 'website_scans' jenkins job.
There were some links that seem to be up at times, but that are
identified by link-checker as broken because of SSL issues.
At least one other link was changed to point to archive.org so
that it doesn't break at some point in the future. We should
probably try to make sure that everything is archived there and
point to those versions when possible.
There are still lots more links to do.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I36868ddf6113e18fa6841427dd635c75445b7bef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
There is no need that the tutorial for flashing firmware has its own
point in the main menu. Thus, move it to the tutorial section.
Change-Id: Ife6d97254af4c006fe01480a78c76303f9cb34bb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
In preperation for CB:62424, replace HTTP links pointing to the flashing
firmware tutorial with file paths to the Markdown files.
Change-Id: I6a271a912348cbe002bc9cced9922ed743e1133c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
While running Sphinx, it shows the warning "document isn't included in
any toctree" for the documents checklist.md and templates.md. These are
not meant to be listed in ToC trees.
Thus, mark them as orphaned to exclude them from ToC trees.
Change-Id: I1ff8f7c24ac9b3c3a120914c0c72ab73e85c4873
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62584
Reviewed-by: Thomas Heijligen <src@posteo.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The QEMU POWER9 target is supported since coreboot version 4.15.
Documentation is available in the tree, but it's not referenced from
the mainboard index page. Fix that.
Change-Id: Ic3b98735840c146cb0bfb122df0e6f762c2beeca
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fix spelling and use the one from their website qemu.org.
Change-Id: I36a88985ce3a7c59b732c1ca3198d86a591de6bd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Supermicro X9SAE target is supported since coreboot version 4.15.
Documentation is available in the tree, but it's not referenced from
the mainboard index page. Fix that.
Change-Id: I5d3d0b5b935f1a3ea353a3d9e39208db7c7895ef
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fix the spelling and use the one from their website supermicro.com
Change-Id: Id630d9d130082fb38f9151e0dfb6f6fbb5a2789d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Move the instructions for flashing coreboot with fwupd to common
directory as the process is identical across all models and variants.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I293acf962b32c81fdf482e0df15363e1cffa39bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There is no reason to use lists to link the checklist and template
document. Thus, link to these documents in their related flowing text.
Change-Id: I9bce0dd6595f1a208e7ea2311a653f9af32530de
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62412
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The list of releases will grow and in the current state each release
moves the section for the upcoming release more down making it less
visible.
Thus, switch both sections, so that the documentation for the
upcoming release is at the top. Also, invert the order of the previous
releases, so that the latest is at the top.
Change-Id: I69987e035f38ae3ca14dbf5c7644d5292106a978
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62411
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The documents for the checklist and template are related to upcoming
releases. Thus, move them to the section for upcoming releases.
Change-Id: Ibe6be506d2833036105b7c86445dca2a6efb7a55
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62410
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The release notes document also contains information about upcoming
releases, not only previous releases. Thus, rename the document in the
main menu and give it a proper title.
Change-Id: I4480c0b6e4be6fcbcb9a00beb0be169a7eed435d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Gerrit Guidelines are related to the contributing process and also
contain documentation which goes beyond "Getting started". Thus, move
them to the "Contributing" section.
Change-Id: I775a79c14562a1f4a9563012aee3b690c0635cc1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
- Remove arrows from google mainboard as requested in the last review.
- Make Feb25 the release date.
- Cosmetic markdown changes - Rewrapping, updated for lines' lengths.
- Add plan to support Resource allocator V3 on the 4.18 branch.
- Add plan to deprecate LEGACY_SMP_INIT after 4.18 release
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Id16925918511fd2277a54faeccfa56e96c6aaae5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62380
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update list of boards that support vboot.
Change-Id: I7f372c5b923018bc1b744fd02d5acc976b03742a
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Clean up the main menu by adding a new entry `Contributing` and moving
all related menu entries below it.
Change-Id: I04ec8a568b716df48ae7f8f826826e8753f5f88b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Clean up the main menu by adding a new entry `Community` and moving all
related menu entries below it.
Change-Id: Ib5df0156edaa739f15e6da8489968448876e1894
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Replace HTTP links with paths to Markdown files where possible.
Change-Id: I0ecca6460105b10b81c4fc014f00235b5d9b861c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Fix formatting when text should be bold.
Change-Id: I7a88ddc0a56dba8c05d0997f37121d0f2cc84ce6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Add a site containing general information for GSoC contributors and
mentors. It was initially copied from https://www.coreboot.org/GSoC.
Change-Id: I5c21d026118cba571dc6b817e89cc4da296a1799
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Add an option to build skiboot as a payload. This makes QEMU Power9
board simpler to use as skiboot is necessary anyway.
Change-Id: I0b49ea7464c97cc2ff0d5030629deed549851372
Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com>
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This patch documents the recommendation as per Intel GPIO BWG on
GPIO PAD lock configuration.
As per GPIO BWG, it's recommended to change the Pad Reset Config
for lock GPP as `Power Good` so that pad configuration and lock
bit can be reset at the same time.
Refer to Intel doc:630603 for details.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3faf5dfc28c8c2dbc322db80a59f44a29002673c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
apcb_v3_edit.py tool edits APCB V3 binaries. Specifically it will inject
up to 16 SPDs into an existing APCB. The APCB must have a magic number
at the top of each SPD slot.
BUG=b:209486191
BRANCH=None
TEST=Inject 4 SPDs into magic APCB, boot guybrush with modified APCB
Change-Id: I9148977c415df41210a3a13a1cd9b3bc1504a480
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This adds a new port for the ASRock H77 Pro4-M motherboard. It is
microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3
SDRAM.
The port was initially done with autoport. It is quite similar to the
ASRock B75 Pro3-M which is already supported by coreboot.
Working:
- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
- Native RAM initialization with four DIMMs of two different types
- PS/2 combined port (mouse or keyboard)
- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub)
- PCIe graphics in the PEG slot
- All three additional PCIe slots
- All rear and internal USB2 ports
- All rear and internal USB3 ports with reasonable transfer rates
- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s)
- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s)
- Rear eSATA connector (multiplexed with one ASM1061 port)
- Console output on the serial port of the Super I/O
- SeaBIOS 1.15.0 to boot slackware64
- SeaBIOS 1.15.0 to boot Windows 10 (needs VGA BIOS)
- Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`)
- External flashing with flashrom-1.2 and a Raspberry Pi 1
- S3 suspend/resume from either Linux or Windows 10
Not working:
- Booting from the two SATA ports provided by the ASM1061
- Automatic fan control with the NCT6776D Super I/O
Untested:
- VBT (it is included, though)
- Infrared header
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use ed25519 keys because recent changes to RSA keys in OpenSSH are
making a mess.
Also update references to the Gerrit UI to match the current version.
Change-Id: Ib13836feb6968307d2c8b3022cb0c859dac89bb8
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
CPLD can be used for board revision determinition.
Remove info about selecting memory type and add Rev 1.4 info
BUG = N/A
TEST = NA
Change-Id: I4bc851f72ae03e98ab1b2e0e04b07ccf6135ebeb
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Private changes on Gerrit are a tricky beast in that they're well hidden
in the UI and a few other places but still reachable under certain
circumstances.
Change-Id: I1c8c6cccfd023bc1d839dc5d9544204c88f89c7e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
While we don't _want_ FSP, we can't get around it sometimes. But when
using it, we can still try to establish best practices to make life
easier for everybody.
Change-Id: I4efd273e4141dc6dc4cf8bdebda9cffd0d7cc1a1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Update Delta Lake document following the publish of OCP blog
and the Wiwynn press release.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I3eaa765bf9918988b4b5cb01e8607a5c27b9bd17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
coreboot 4.15 has just been released, so it's neither "upcoming" nor
"planned" anymore.
Change-Id: I287e40deec5877764e511885e3268b606caff597
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59121
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update list of boards that support vboot.
Change-Id: Id5d4d18202bf85c5ba407efd690eee5cba88a8a7
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58975
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change-Id: I6c8327a7cf47217d32359b304b21e806c10dcc62
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Most of the System76 boards have now been merged.
Change-Id: I0353b28c1df3da8be961cb43225dcf9e30b47d16
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Code coverage requires `lcov`, so update the docs to call it out
specifically.
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Ie2898faa5188a7174c4e56ba34f1a4f02f939b03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
As of 2020-07-21 their website says "we'll stop any device produce
and won't have a date to return (if we return)."
While wishing them best of luck (and welcome them back to the list
of distributors), let's take them off the list while they don't
ship hardawre.
Change-Id: Ia110d0e25bf73c3d7db270b0c2c0e23b99fc36ef
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The coding style doc isn't short, so scrap that, and it's specific to
the C parts of our tree, so add that.
Change-Id: Ib1ef7c1a96ff40f0cfbae7d22a47a95128981eb8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58381
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looks like nothing references this example. Remove it. If one needs an
example, there's several mainboards which contain an I/O trap handler.
Change-Id: I4a238fbf354926cb6568e1709bfb79cc546dfd73
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: If2a8e97911420c19e9365d5c28810b998f2c2ac8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58078
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Angel Pons