To have both the PCI function number and the register offset into the
config space of that function of the data fabric device in the data
fabric register definitions, introduce and use the DF_REG_ID, DF_REG_FN
and DF_REG_REG macros. The DF_REG_ID macro is used for register
definitions where both the function number and the register offset are
specified, and the DF_REG_FN and DF_REG_REG macros are used to extract
the function number and the register offset from the register defines.
This will allow having one define for accessing an indexed group of
registers that are on different functions of the data fabric device.
TEST=MMIO resources read from the data fabric's MMIO decode registers
don't change on Mandolin and the ACPI CRAT table is also identical.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I63a284b26081c170a217b082b100c482f6158e7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76886
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Debug messages shown during IDE initialization are streamlined as
follows:
"Primary IDE interface" (and similar) are shortened to
"Primary interface".
We don't need to see "IDE" twice as messages are already prefixed.
Refactor "IDE: (Primary) IDE interface: (on)" into
"IDE: (Primary interface): (on)" to allow compiler to deduplicate
component strings, also used later in messages re UDMA/33.
This reduces uncompressed string size by 32 bytes and allows ramstage
to compress a wee bit better.
Change-Id: I16f5c2b3775c5a73b83d83817d7075e944089a12
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73331
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I don't get around to do proper full reviews of SIO patches since maybe
3 years, so I better remove myself from the maintainers list for that
part of the coreboot tree. If anyone else wants to take this over,
please go ahead. I can still help with some advice and general ideas in
that area, but even the "odd fixes" status that I downgraded the
maintenance status of that sub-tree to some time ago was a bit too
optimistic.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic56b710ffe68c6e407786d551cafac698e8bb61d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77063
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When wildcards are used in toplevel Makefile.inc it ends up appending
all items including regular files into subdirs-y which then are treated
as directories in "evaluate_subdirs" with "Makefile.inc" appended to
them. Check for a valid path (existing Makefiles.inc) before attempting
to process it.
Change-Id: I368b5b9a7ece3c675674fcb24303276a87c15668
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Since it was the only super I/O in the serverengines folder, also drop
the parent folder.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I610c94bc100c9d5558da442b2847d8f26de07820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77064
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix ethernet MAC address configuration. Currently, coreboot would
use ethernet_mac0 for both ports when setting the system's MAC
address. Instead, set the right device_index for the second controller
to pick up ethernet_mac1.
BUG=b:294856127
TEST=boot device and observe two different MAC addresses on the ethernet
ports.
Change-Id: I5ff6d62d2f837a120f7095f9b9aed487e6c5aee4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77044
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This upgrades the tint payload to 0.07 version. The sources are
similar enough so that ..._libpayload.patch could be simply git-moved.
Change-Id: I0f6de3d0410e6d838fe49330d98620c877a0d2c7
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76820
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the RPL CPU power limits and system power limits based on
the suggestion of the thermal team for RPL SKUs.
The PL4 value suggested by the thermal team which is different from the reference document 686872.
BUG=b:292471206
BRANCH=firmware-brya-14505.B
TEST=built and booted into OS.
Change-Id: Ia030d13ca276c5e8340ae3b20d6e169bb162751d
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76769
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Restore the tint build system compatibility with the current version
of buildgcc script while preserving the backwards compatibility.
Change-Id: I45d3454b4527ee81c3927a5b3da2e9067c530fb0
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76819
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without setting these GPIO bits, you /can/ power on your board after
powering it down again. This includes after cutting the power.
The only way to recover from this is to pull the CMOS battery and cut
the power for 15mins. Then make sure you don't do this GPIO trickery or
you end up with the same state of basically an unresponsive "dead"
mainboard. So flash the chip before you pull the battery.
One small workaround I found when you like to flash from the system, is
to press the power button with 1 second after you enable power to the
board. In this small timeframe, apparently the superio chip didn't
intialise/restore/gets set with the settings that make it never want to
power on again. The other workaround is to connect the appriopriate
pins on the ATX power connector to force power to the mainboard.
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: I4c9df200ba3ec5f315ad3d184588551d29fa68ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Use C99 flexible arrays instead of older style of one-element or
zero-length arrays.
It allows the compiler to generate errors when the flexible array does
not occur at the end in the structure.
Change-Id: I19c029968584fedbb6749e66c7ea2f74a7d580f4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Copy jack detect GPIO config of NAMI variant, which uses the same
codec for the external jack/mic. The internal pull-up isn't needed,
and fixes issue of high CPU usage under Windows.
TEST=build/boot google/rammus, verify jack detect functional under
both Win11 and Linux 6.x, no high CPU usage from excessive interrupts.
Change-Id: Ifbe23a6b33343e54b43879a8971c7cb6475cf1f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76947
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Channel portalling has been disabled for the matrix.org-libera.chat
bridge[1]. Hence, we created a new Matrix channel #coreboot:matrix.org
(that is plumbed to the IRC channel).
[1] https://libera.chat/news/matrix-deportalling
Change-Id: I896bfed71790988503dc8229fe9b34e175046dbf
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76864
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Once platform code has filled in the (legacy) ACPI PM register
map, added function will fill in the extended entries in FADT.
TEST=samsung/lumpy and amd/mandolin FADT stays unchanged.
Change-Id: I90925fce35458cf5480bfefc7cdddebd41b42058
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
The first platform samples came with IT8786E. The production units
switched to IT8784E in the final design.
Change the code to use IT8784E and reflect the proprietary firmware
configuration of the SIO chip.
TEST=Boot Ubuntu 22.04 on Protectli VP4670 (vault_cml) and dump the
configuration with superiotool and compare the configuration with
proprietary firmware.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5dc6669b592484e445c8c4bbe95d73f0a9f0392e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74175
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
IT8784E is basically a IT8786E stripped from serial ports 3-6.
The patch creates a chip directory for IT8784E used by
protectli/vault_cml platforms.
TEST=Boot Ubuntu 22.04 on Protectli VP4670 (vault_cml) and dump the
configuration with superiotool and compare the configuration with
proprietary firmware.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ibe01358611f3ce3f155ddb01a7d177a3ff75765e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Add ramstage.c in Makefile.inc and update boxy power limits in
Boxy ramstage.c.
BUG=b:290293153
TEST=emerge-dedede coreboot and check psys and PLx value on boxy
Change-Id: I4257dab358f066ebd13b6f251e8a5258a72fbd39
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76877
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Threatening or initiating legal action against the maintainers of our
infrastructure or projects (all projects hosted on our infrastructure)
is a huge stressor to those maintainers.
To underline that severity, such threats or action will lead to an
immediate ban from our infrastructure as agreed on the leadership
meeting of 2023-05-31.
There may be legitimate legal action to take in certain cases, and
it's always possible to unban people, but given the severity provide
warning that we'll opt for a "ban first, sort out later" approach.
Change-Id: Ifa865487dc81ed3797fe60e5cef737c57dd85fea
Signed-off-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75554
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Problem:
Me: $ util/abuild/abuild -t asus/p2b -b p2b-ls
abuild: No such target: asus/p2b, variant: p2b-ls
Cause: We identify boards and variants using path names in tree, so
I type in the test command above. abuild identifies all board variants
the Kconfig way, in all caps and all underscores.
Result: Expectation gap and abuild can't find anything where we expect
it to. All variants with a hyphen in their names are affected.
Fix: Add a substitution to replace hyphens with underscores.
Test: I get my abuild with the command above, even a variant-specific
test config works.
Change-Id: I10d5b471dac41c50a85c4a309ec561b02687bb9a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41918
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Use ARM architectual timer by initializing frequency to 13 MHz. Since
system timer is the source of the architectual timer, we also call
`timer_prepare` in `init_timer`.
BUG=b:229800119
TEST=run `suite:faft_bios` to verify the firmware stability.
check timestamps by cbmem.
Cq-Depend: chromium:4747539
Change-Id: I8b1348044e4c92984510604b7f61611e13284d86
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76919
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pull in commit adding signed verstage files for Google mainboards
zork, guybrush, and skyrim.
Change-Id: Ia3024622a622285b7b2a1f4eef88cf0e2927424e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
All boards based on brya will have GFX devices to represent DRM
connectors in the kernel's /sys/class/drm/.
There should be no functional impact with or without this patch.
BUG=b:277629750
TEST=emerge-brya coreboot
Change-Id: I11afa9e8a1c8bf9f57bf6d195f07531182bd36f1
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the device and soc directories that don't already have an
SPDX license line at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I89c05c7c1c39424de2e3547c10661c7e3f58b8f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the mainboard directory that don't already have an SPDX
license line at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the drivers directory that don't already have an SPDX
license line at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8442bc18ce228eca88a084660be84bcd1c5de928
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68980
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
To help identify the licenses of the various files contained in the
coreboot source, we've added SPDX headers to the top of all of the
.c and .h files. This extends that practice to Makefiles.
Any file in the coreboot project without a specific license is bound
to the license of the overall coreboot project, GPL Version 2.
This patch adds the GPL V2 license identifier to the top of all
makefiles in the cpu directory that don't already have an SPDX
license line at the top.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I3033f2a9eebc75220f7666325857b3ddd60c8f75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68979
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Select ENABLE_TCSS_USB_DETECTION for non-ChromeOS builds, to enable
booting from TCSS USB-C ports.
TEST=build/boot google/banshee, verify able to boot from all USB ports
using edk2 payload.
Change-Id: I998cc4a40950f43b4c511ead93ccc02c56c8367c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76945
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select ENABLE_TCSS_USB_DETECTION for non-ChromeOS builds, to enable
booting from TCSS USB-C ports.
TEST=build/boot google/drobit, verify able to boot from USB ports using
edk2 payload.
Change-Id: Ic6ab84dd5d1b980296eac043917d2cc7f14a5536
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Inspect all type-C USB ports, check if there is a USB device attached,
and if so, send the connection request to the PMC. This allows for any
attached USB2/USB3 devices to be used for booting by the payload.
Since this functionality is only needed by ChromeOS devices with TCSS
running upstream coreboot, introduce a new Kconfig to guard its use.
Boards needing it will select it in subsequent commits.
TEST=tested with rest of patch train
Change-Id: I69522dbcc8cae6bbf41659ae653107d0e031c812
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72909
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variable 'i' is unsigned, so use %zu vs %zd.
Change-Id: I5f5b28796b30285e81a94c37e686a9e763cab204
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76943
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Similarly to te_relocate(), on success pe_relocate() should return 0.
It has never been an issue so far as pe_relocate() return value is not
tested.
Change-Id: I8e531662952d12e1f0ffa34042dab778ea602bfc
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76891
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Report CPU C10 state over eSPI so that the EC can use Virtual Wires to
detect if PECI can be used.
Change-Id: I301361f35caee8ba1c3fd9227219603897add92b
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76910
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When lemp9 was converted to a variant in CB:64528, the Makefile was not
updated to handle the variant-specific `romstage.c`. This, as would be
expected, caused memory init errors and broke boot on CML-U boards.
Tested lemp9 boots to payload again.
Fixes: 5b7b04c938 ("mb/system76/cml-u: Convert lemp9 to a variant")
Change-Id: Ibc11d69a1662df653e6553421d67a9cd1b1d03e2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
BUG=b:279097356
TEST=On dibbi:
- flash OS 15449.0.0 (where suspend is broken due to b:274531972)
- run `suspend_stress_test --count=1 --suspend_max=30 --suspend_min=28`
- check the AP wakes up immediately when the EC detects a sleep hang
Change-Id: I24a2aa5de1f76e6dd1c1ce726b648583756e5e55
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76938
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add PLx from JSL PDG(ID: 613095) in boxy devicetree.
BUG=b:290293153
TEST=emerge-dedede coreboot and read correct value on boxy CPU log:
CPU TDP = 6 Watts, CPU PL4 = 60 Watts
Change-Id: I7b063dc235fb714ba47eb620b914f2f9e92a2715
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76876
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The prefix POSTCODE makes it clear that the macro is a post code.
Hence, replace related macros starting with POST to POSTCODE and
also replace every instance the macros are invoked with the new
name.
The files was changed by running the following bash script from the
top level directory.
header="src/soc/amd/common/block/include/amdblocks/post_codes.h \
src/include/cpu/intel/post_codes.h \
src/soc/intel/common/block/include/intelblocks/post_codes.h"
array=`grep -r "#define POST_" $header | \
tr '\t' ' ' | cut -d ":" -f 2 | cut -d " " -f 2`
for str in $array; do
splitstr=`echo $str | cut -d '_' -f2-`
grep -r $str src | cut -d ':' -f 1 | \
xargs sed -i'' -e "s/$str/POSTCODE_$splitstr/g"
done
Change-Id: Id2ca654126fc5b96e6b40d222bb636bbf39ab7ad
Signed-off-by: Yuchen He <yuchenhe126@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76044
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
_DSD "StorageD3Enable" property is needs to be set under the root
port in the DSDT or SSDT. The ACPI _DSD method is the preferred way
to opt D3hot support for storage devices.
This also bypasses the low LTR from SSD that blocking S0i2.2
LTR/latency SoC requirement.
Name (_DSD, Package () {
ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"),
Package () {
Package (2) {"StorageD3Enable", 1},
// 1 - Enable; 0 - Disable
}
}
)
BUG=b:289028958
TEST=Check code compiles & boot rex, and verify the "StorageD3Enable"
SSDT entry.
Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76835
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch configures external V1p05/Vnn/VnnSx rails for Craaskov
to follow best practices for power savings – untested though.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
BUG=b:290165011
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ibaf6a285788e26688d3d42691ab40052ef6d6cdb
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76926
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DPTF parameters were verified by the thermal team.
Based on thermal table in 290705146#comment11.
Set "tcc_offset" = "8"
BUG=b:290705146
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I2d9e1ad2e2fa98757d76578956101a482073885e
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76712
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
To be consistent with other boards setting the keyboard backlight at
boot.
Change-Id: I40d8ebe468a967f0dfe1e82bff9c63f1986699c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76942
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This feature was originally present and then dropped, but turns out
that users prefer it. Set the backlight to 50% in romstage, back to
zero in ramstage; skip enabling on the S3 resume path.
TEST=build/boot google/eve, verify keyboard backlight turns on/off
as expected.
Change-Id: I33af888d614010538f69512bbd052ed2b83fcaa5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move the jack detect GpioInt resources under the codec (where they
belong), but also leave a copy under LPEA for since the Linux drivers
(incorrectly) require them there. Add pin list for Windows' SST driver.
Adapted from the Intel ValleyView edk2 ACPI reference code.
TEST=build/boot Win11, Linux on google/swanky; verify audio functional
OOTB under Linux, under Windows with coolstar's drivers.
Change-Id: I51c07013fc20f07d2fd3639f7fbc2af0e0e490a0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76795
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
- add HRV and GpioIO for coolstar's windows drivers
- fix interrupt type for TI jack detect switch
TEST=build/boot Win11, Linux on google/cyan; verify audio working
OOTB under Linux, under Windows with coolstar's audio drivers.
Change-Id: I6bf6bb9e9989ca8f42436800666d95dd05799838
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76800
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Most of the components of this laptop are tested to work,
which is listed in the documentation.
Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46630
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Felix Held