sata_devslp_disable was set to work around some buggy SSD
firmware, but as it's disabled by default in both Linux and
Windows, no reason to disable at the firmware level when
many properly-functioning SSDs can take advantage of power
savings.
Change-Id: Ib15f8b51db19b3d9d2e135f85c71a15a45a2ffbd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Update camera sensor detail to OV 13858
Also update i2c address of OV5670
BUG=None
TEST= Build & boot to ChromeOS. Check for both the camera detection.
Change-Id: I3b6192815201f605d3ebdb4bf54db26a8e837b35
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fix for all Sandy-Bridge and Ivy-Bridge devices.
Remove unused option "hyper_threading".
Increase CMOS checksum range to cover all user adjustable settings.
Change-Id: I02f7af13d9c82d7f531d4b49b3bc0e5a20c14b55
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is to align with the SD_CD GpioInt setting in acpi
BUG=b:62067569
TEST=checked unused interrupt on SD_CD does not happen after s3 resume
Change-Id: I40aefcb0f571e7f6773a6d20226f357707aa041a
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/20001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently, there is no macro to set GPIO interrupt trigger mode.
The purpose is to make coreboot set same trigger mode as GpioInt
BUG=b:62067569
TEST=checked unused interrupt on SD_CD does not happen after s3 resume
Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/19992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Disable unused bridges that are not marked as hot-plugable.
Reduces idle power consumtion by ~200mWatt for each port.
Tested on Lenovo T430.
Change-Id: I6ee5e5f33824acdbca0f6ed28e90beab7fe10002
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19818
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Add a method to get the state of a bridge device.
Return true if at least one enabled device on the secondary
bus is found.
Useful to disable non hotplugable bridges without any devices attached.
Change-Id: Ic8fe539d233031d4d177b03dd2c03edb5ab8c88d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Like HAVE_VGA_TEXT_FRAMEBUFFER, these are selected by graphics drivers
that support a linear framebuffer. Some related settings moved to the
drivers (i.e. for rockchip/rk3288 and nvidia/tegra124) since they are
hardcoded.
Change-Id: Iff6dac5a5f61af49456bc6312e7a376def02ab00
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Rename it to HAVE_VGA_TEXT_FRAMEBUFFER.
* Let drivers select it if they are in charge.
* Don't select it on the mainboard level if a driver handles it.
Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The separate directory was the old way of handling variant boards.
Update bakersport_fsp to the new method. All of the other pieces
were already moved into bayleybay_fsp.
Change-Id: I5712c1b399570bd7ab7fc9e42af25fbf15a0ba78
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/19077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Move the inline keyword in between the static keyword and the return
type.
Change-Id: Ibacc5ee9fabff7fec2abd5534312cf3ab1bb28cf
Signed-off-by: Logan Carlson <logancarlson@google.com>
Reviewed-on: https://review.coreboot.org/19991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Light sensor isn't used and ACPI already removed, so disable
I2C5 bus interface as well.
Disable I2C6 for devices without a touchscreen
Change-Id: Ib0e041ae9131615ef1140bad064de5aae91f8ee4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
Change-Id: Iad947ae2cd541d3407455b218c2b352b9a373718
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19973
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add device/address stub for XHCI USB port 7.
Stub data will be supplemented by board-specific info
added in subsequent commits.
Change-Id: Iae874a9ba01e9428e07cf7ff15e663365b2354a9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add device/address stubs for XHCI USB ports 7/8, 10-15.
Stub data will be supplemented by board-specific info
added in subsequent commits.
Change-Id: Ice86bd226a70bd5996430e7a68a026cc825ba187
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19968
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove MONOTONIC_TIMER_MSR selection from mainboard
Konfigs, as it only does a reduntant selection of
HAVE_MONOTONIC_TIMER config, already selected under
skylake soc Kconfig.
Change-Id: Ib3177ceb9e8b6c16ce0e437a4a02b94f215af58f
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/20002
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
This board is almost identical to D510MO, the only differences are
some differences in populated connections, CPU with less L2 cache and
a 10/100 Realtek NIC.
The vendor uses the very same binary for both D510M0 and D410PT.
Change-Id: I220515365b69e785ef249c4e3a9af5f7fddf02f9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The IO region defined for EC_HOST_CMD_REGION1 was incorrectly
using EC_HOST_CMD_REGION0 for the range maximum so the region
was showing a minimum of 0x880 and a maximum of 0x800.
Both min and max should report the same value as this region
is fixed and cannot be relocated by the OS.
Change-Id: I387b1c36aa115e03d0c6f9939eb13c93b14ad909
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use register name instead of magic value.
Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In get_region, ifdtool assigns a not-known-to-be-aligned
pointer to a uint32_t *. Now you know and I know that it is
almost certainly aligned, but clang on OSX doesn't like this,
and it's a dicey thing to do in any event, just waiting
to hit someone hard at some future date.
Assign the pointer to a void * and use memmove to copy
the value to a uint32_t.
This usage is more portable to all little-endian architectures,
now, but is still not endian-safe. I doubt we'll ever care.
Change-Id: Ifb2f260c3363ab0f5b4a59e5a4e0b5ecf049fa96
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/19921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Each slippy variant has slightly different USB port config;
data for falco and leon to be added once available
Change-Id: Icc3b5b1161f62ac0b840380679acafeff363cf45
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
All beltino variants use the exact same USB port layout.
Change-Id: If5b540949ea071f7165876e12ac1ef50e62d2b22
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add device/address stubs for XHCI USB ports 7, 10-13.
Stub data will be supplemented by board-specific info
added in subsequent commits.
Change-Id: I7d2f93351435cccd62e8fe4d95ad3467aa09de69
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19965
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
Change-Id: If63d5637a0469eeace0d935cca961e8d04fdfb1a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Move inclusion of mainboard.asl after southbridge asl files
so scopes referenced in usb.asl are valid.
Change-Id: I58ea0b43f7f2c2692630df3bdb06af92566c1202
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add ACPI method GPLD to generate port location data when
passed visiblity info. Will be used by _PLD method in
board-specific USB .asl files.
Change-Id: Ib83660d6548112ceb6c75a31e5ce6c4a6041ccfb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Port 0 is connected to SD-card reader.
Don't mark it as hot-plugable.
Change-Id: I5d3d4c7541683a6c09aac47ca251a6dad23ad1ab
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
To unify the hwinfo handling along all Siemens MC boards the hwinfo
files have to be removed from the mainboard directory. They will be added
to cbfs in site-local/Makefile.inc.
Change-Id: Ia3dcb2e0118527b37aed872740273c4fa7004aef
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The prior used RTC PCF8523 is replaced with RX6110SA on this mainboard.
Switch to the new RTC in Kconfig and adapt devicetree to the new chip.
Change-Id: I7c4911191cae254900f9a958da42ecd18497484c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The driver for the RTC RX6110SA is designed to be used with I2C bus.
This patch adds the possibility to use SMBus operations to access the
RTC. For this purpose the Kconfig switch RX6110SA_USE_SMBUS is added. It
is not enabled per default so that I2C will be used. One can set this
switch on board level to use SMBus instead.
Change-Id: I4827ae2c544e8002399d94a1159acacd8176c5e9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/19978
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modify the DPTF configuration on Eve to relax the severe throttling that
is currently applied and allow performance testing to see better results.
BUG=b:35581264
TEST=performance tests show better results and thermal tests still pass.
Change-Id: I0838f4ec3026bc8bac814698043fa97cf6772cb4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Instead of having the SMI handler power off the touchscreen on the
way into suspend add power resource controls to the ACPI device so
the power is managed by the kernel instead of the BIOS.
BUG=b:35581264
TEST=manual testing on Eve to ensure that the touchscreen is still
functional at boot and after suspend/resume, and that it does not
draw power in suspend.
Change-Id: Id9a98807d24bbc7dff32408f3d113f6fad5bc023
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Caching is a very architecture-specific thing, but most architectures
have a cache in general. Therefore it can be useful to have a generic
architecture-independent API to perform simple cache management tasks
from common code.
We have already standardized on the dcache_clean/invalidate naming
scheme that originally comes from ARM in libpayload, so let's just do
the same for coreboot. Unlike libpayload, there are other things than
just DMA coherency we may want to achieve with those functions, so
actually implement them for real even on architectures with
cache-snooping DMA like x86. (In the future, we may find applications
like this in libpayload as well and should probably rethink the API
there... maybe move the current functionality to a separate
dma_map/unmap API instead. But that's beyond scope of this patch.)
Change-Id: I2c1723a287f76cd4118ef38a445339840601aeea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
This patch adds a simple function that can be used to check if
CAR_GLOBALs are currently being read from CAR or from DRAM.
Change-Id: Ib7ad0896a691ef6e89e622b985417fedc43579c1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
The Tegra210 SoC never had a proper cpu_reset() implementation, so it's
pointless to pretend there is one. Most ARM SoCs/boards only define
hard_reset() at the moment anyway, so let's stick with that.
Change-Id: I40f39921fa99d6dfabf818e7abe7a5732341cf4f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
coreboot and libpayload currently use completely different code to
perform a full cache flush on ARM64, with even different function names.
The libpayload code is closely inspired by the ARM32 version, so for the
sake of overall consistency let's sync coreboot to that. Also align a
few other cache management details to work the same way as the
corresponding ARM32 parts (such as only flushing but not invalidating
the data cache after loading a new stage, which may have a small
performance benefit).
Change-Id: I9e05b425eeeaa27a447b37f98c0928fed3f74340
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Place it into new edid_fill_fb.c, and invert the logic of the Kconfig
guard (NATIVE_VGA_INIT_USE_EDID is now !NO_EDID_FILL_FB). It has to be
selected by all drivers that use MAINBOARD_DO_NATIVE_VGA_INIT but pro-
vide their own fill_lb_framebuffer() implementation.
Change-Id: I90634b835bd8e2d150b1c714328a5b2774d891bd
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Specification says to do CAR teardown as part of AmdInitPost().
Move initializing the final AGESA heap storage to AmdInitEnv()
so that its work is not lost even if AMD_DISABLE_STACK does
invalidation without writeback.
Change-Id: Icf0ec74c390e60122d0b312b5f09f46bb930e085
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
As the comment above the change indicates, and per ACPI spec,
_DSS has one argument.
Change-Id: Ic05832d412cd0c89ed3a275c4db694a9118dac28
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Via/VX800 was the last chip not defining it.
Change-Id: Idd03f48bed881a5846b1bb3bf29254450d6cff3b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Get rid of mainboard_io_trap_handler.
The only purpose is to enable tp-smapi, but is already done on all
boards in h8_enable, as of devicetree setting config0.
Change-Id: I33fd829a7e34aefa8f76ca6020cc8e802f7aab17
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Instead of assuming the mapping of dimm number to SPD SMBus address,
allow the mainboard to provide its own mapping. That way, global
resources of empty SPD contents aren't wasted in order to address
a dimm on a mainboard that doesn't meet the current assumption.
Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Matt DeVillier