Commit graph

812 commits

Author SHA1 Message Date
Kyösti Mälkki
029cebc7cd postcar_loader: Support LATE_CBMEM_INIT boards
Create postcar_frame object without placing stack in CBMEM.
This way same cache_as_ram.inc code can be used unmodified.

Change-Id: Ic5ed404ce268ee881e9893dd434534231aa2bc88
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17700
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-09 23:54:34 +01:00
Aaron Durbin
b21e362e93 cpu/x86: allow AP callbacks after MP init
There are circumstances where the APs need to run a piece of
code later in the boot flow. The current MP init just parks
the APs after MP init is completed so there's not an opportunity
to target running a piece of code on all the APs at a later time.
Therefore, provide an option, PARALLEL_MP_AP_WORK, that allows
the APs to perform callbacks.

BUG=chrome-os-partner:60657
BRANCH=reef

Change-Id: I849ecfdd6641dd9424943e246317cd1996ef1ba6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17745
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2016-12-08 21:39:43 +01:00
Kyösti Mälkki
6f66f414a0 PCI ops: MMCONF_SUPPORT_DEFAULT is required
Doing PCI config operations via MMIO window by default is a
requirement, if supported by the platform. This means chipset
or CPU code must enable MMCONF operations early in bootblock
already, or before platform-specific romstage entry.

Platforms are allowed to have NO_MMCONF_SUPPORT only in the
case it is actually not implemented in the silicon.

Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17693
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-07 12:59:28 +01:00
Kyösti Mälkki
140087f84f CPU: Declare cpu_phys_address_size() for all arch
Resource allocator and 64-bit PCI BARs will need it and
PCI use is not really restricted to x86.

Change-Id: Ie97f0f73380118f43ec6271aed5617d62a4f5532
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17733
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06 20:53:45 +01:00
Kyösti Mälkki
cd6d281fbe CPU: Move SMM prototypes under x86
Change-Id: Iefbc17dcfcf312338d94b2c2945c7fac3b23bff6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17732
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-12-06 20:53:30 +01:00
Kyösti Mälkki
d8d43ba6ac PCI ops: Rename pcie_xx() to pci_mmio_xx()
Change-Id: I7fa65197b8165b9b0b74937f9ba455c48308da37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17530
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06 20:46:13 +01:00
Kyösti Mälkki
48c389e69e PCI ops: Define read-modify-write routines globally
Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17690
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06 20:45:22 +01:00
Kyösti Mälkki
154768b902 intel PCI ops: Remove explicit PCI MMCONF access
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.

All these platforms now have MMCONF_SUPPORT_DEFAULT.

I liked the style of code in pci_mmio_cfg.h more, and used those to
replace the ones in io.h.

Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17689
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-06 20:44:37 +01:00
Aaron Durbin
d008413a3c arch/x86: cache postcar in stage cache
Stash and reload postcar stage in the stage cache for increased
S3 resume speed. It's impact is small (2 ms or so), but there's
no need to go to the boot media on resume to reload something
that was already loaded. This aligns with the same paths we take
on ramstage as well.

Change-Id: I4313794826120853163c7366e81346858747ed0a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17649
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01 08:17:19 +01:00
Aaron Durbin
6c191d8af4 romstage_handoff: add helper to determine resume status
Instead of having callers query the romstage handoff resume
status by inspecting the object themselves add
romstage_handoff_is_resume() so that the same information
can be queried easily.

Change-Id: I40f3769b7646bf296ee4bc323a9ab1d5e5691e21
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17647
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-12-01 08:16:27 +01:00
Martin Roth
f76303e29e Build system: Update HAVE_CMOS_DEFAULT
- Don't build the cmos.default file into cbfs if USE_OPTION_TABLE
isn't specified.
- Don't allow HAVE_CMOS_DEFAULT if HAVE_OPTION_TABLE isn't set.

Change-Id: I92401e892f09fc95d4b3fd7418cdbd10ed033fa8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17454
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-28 18:58:15 +01:00
Naresh G Solanki
ab77cd4785 arch/x86/acpigen: Write DSM method with multiple UUID's
Enable generic way of writing DSM method which can write acpi table for
multiple UUID's.

Change-Id: Ic1fbdc0647e8fdc50ffa407887feb19a63cb48e4
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17424
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-11-24 05:01:37 +01:00
Aaron Durbin
ebbd12f8bc arch/x86: don't create new gdt in cbmem for relocatable ramstage
When running with relocatable ramstage, the gdt loaded from c_start.S
is already in CBMEM (high memory). Thus, there's no need to create
a new copy of the gdt and reload.

Change-Id: I2750d30119fee01baf4748d8001a672d18a13fb0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17504
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-21 16:45:10 +01:00
Kyösti Mälkki
78c5f0cc02 arch/x86 GDT: Fix orphan debug output
On S3 resume path, CBMEM_ID_GDT already exists but we only printed
the final "ok" string. Always tell GDT is about to be moved.

Change-Id: Ic91c5389cf4d47d28a6c54db152c18541c413bc1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17500
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-20 03:10:32 +01:00
Naresh G Solanki
05abe4351b arch/x86/acpigen: Implement acpigen functions to return integer & string
Add ACPI method to return integer & string.

Change-Id: I2a668ccadecb71b71531e2eb53a52015fca96738
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17450
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-17 21:09:27 +01:00
Naresh G Solanki
c70cc4d70d arch/x86/acpigen: acpigen buffer size fix
In function definition of acpigen_write_byte_buffer, buffer size written
using acpigen_emit_byte gives wrong results in generated AML code for
buffer size greater than one.

Write buffer size using acpigen_write_integer as per ACPI spec 5.0
section 20.2.5.4 BufferOp.

Change-Id: I0dcb25b24a1b4b592ad820c95f7c2df67a016594
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17444
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-11-17 09:52:54 +01:00
Furquan Shaikh
1fc6bb9382 arch/x86/acpigen: Fix acpigen for If (Lequal (...))
acpigen_write_if_lequal is used to generate ACPI code to check if two
operands are equal, where operand1 is an ACPI op and operand2 is an
integer. Update name of function to reflect this and fix code to write
integer instead of emitting byte for operand2.

TEST=Verified by disassembling SSDT on reef that ACPI code generated for
If with operand2 greater than 1 is correct.

If ((Local1 == 0x02))
{
	Return (0x01)
}
Else
{
	Return (Buffer (One)
	{
		0x00                          /* . */
	})
}

Change-Id: If643c078b06d4e2e5a084b51c458dd612d565acc
Reported-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17421
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-16 01:08:06 +01:00
Kyösti Mälkki
9d6f365643 ACPI S3: Remove HIGH_MEMORY_SAVE where possible
Add implementation to use actual requirements of ramstage size
for S3 resume backup in CBMEM. The backup covers complete pages of 4 KiB.

Only the required amount of low memory is backed up when ACPI_TINY_LOWMEM_BACKUP
is selected for the platform. Enable this option for AGESA and binaryPI, other
platforms (without RELOCATABLE_RAMSTAGE) currently keep their romstage ramstack
in low memory for s3 resume path.

Change-Id: Ide7ce013f3727c2928cdb00fbcc7e7e84e859ff1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15255
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-11-09 20:52:07 +01:00
Naresh G Solanki
8535c66873 arch/x86/acpigen: Add OperationRegion & Field method
Add acpigen_write_opregion that generates ACPI AML code for OperationRegion,
region name, region space, region length & region size are inputs.

Add acpigen_write_field that generates ACPI AML code for Field.
Operation region name & field list are inputs.

Change-Id: I578834217d39aa3b0d409eb8ba4b5f7a31969fa8
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17113
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
2016-11-07 20:35:12 +01:00
Furquan Shaikh
4a2cfad13b arch/x86/acpigen_dsm: Add support for DSM types
Currently, the only supported DSM type is I2C
HID(3CDFF6F7-4267-4555-AD05-B30A3D8938DE). This provides the required
callbacks for generating ACPI AML codes for different function
identifiers for I2C HID.

BUG=chrome-os-partner:57846

Change-Id: Ia403e11f7ce4824956e3c879547ec927478db7b1
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17091
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-25 00:13:32 +02:00
Furquan Shaikh
c00bd18b13 arch/x86/acpigen: Add support for _DSM method generation
Add acpigen_write_dsm that generates ACPI AML code for _DSM
method. Caller should provide set of callbacks with callback[i]
corresponding to function index i of DSM method. Local0 and Local1
should not be used in any of the callbacks.

BUG=chrome-os-partner:57846

Change-Id: Ie18cba080424488fe00cc626ea50aa92c1dbb199
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17090
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-25 00:13:16 +02:00
Furquan Shaikh
9b39adb454 arch/x86/acpigen: Add more functions to ACPIGEN library
1. If (LEqual (Op1, Op2))
2. ToBuffer (src, dst)
3. ToInteger (src, dst)
4. Buffer (n) { op1, op2 .... }
5. Return ( )

BUG=chrome-os-partner:57846

Change-Id: I24fe647c690b2dd4849f0c53b2672ac7a2caa2de
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17088
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-25 00:10:05 +02:00
Furquan Shaikh
0a48aee795 arch/x86/acpigen: Add support for interacting with GPIOs
Since reading/toggling of GPIOs is platform-dependent task, provide an
interface with common functions to generate ACPI AML code for
manipulating GPIOs:
1. acpigen_soc_read_rx_gpio
2. acpigen_soc_get_tx_gpio
3. acpigen_soc_set_tx_gpio
4. acpigen_soc_clear_tx_gpio

Provide weak implementations of above functions. These functions are
expected to be implemented by every SoC that uses ACPI. This allows
drivers to easily generate ACPI AML code to interact GPIOs.

BUG=chrome-os-partner:55988

Change-Id: I3564f15a1cb50e6ca6132638447529648589aa0e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17080
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-24 17:44:15 +02:00
Furquan Shaikh
fcc7a04cc8 arch/x86/acpigen: Add new functions to acpigen library
Add functions to support generation of following AML operations:
1. PowerResource
2. Store
3. Or
4. And
5. Not
6. Debug
7. If
8. Else
9. Serialized method

BUG=chrome-os-partner:55988

Change-Id: I606736b38e6a55ffdc3e814b6ae0fa367ef7595b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17079
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-10-24 17:44:00 +02:00
Furquan Shaikh
e4e9b94db1 arch/x86/acpigen: Clean up acpigen library
Instead of using hard-coded values for emitting op codes and prefix
codes, define and use enum constants. With this change, it becomes
easier to read the code as well.

BUG=chrome-os-partner:55988

Change-Id: I6671b84c2769a8d9b1f210642f3f8fd3d902cca2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17078
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-24 17:43:47 +02:00
Elyes HAOUAS
7d87e767b6 src/arch: Remove whitespace after sizeof
Change-Id: Ia2fc3d5ea88d61ba7c4a1daebfe74a24948c8f6e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07 18:08:48 +02:00
Furquan Shaikh
028200f75f x86/acpi_device: Add support for GPIO output polarity
Instead of hard-coding the polarity of the GPIO to active high/low,
accept it as a parameter in devicetree. This polarity can then be used
while calling into acpi_dp_add_gpio to determine the active low status
correctly.

BUG=chrome-os-partner:55988
BRANCH=None
TEST=Verified that correct polarity is set for reset-gpio on reef.

Change-Id: I4aba4bb8bd61799962deaaa11307c0c5be112919
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/16877
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2016-10-07 18:05:30 +02:00
Furquan Shaikh
35c01bc4e0 x86/acpi_device: Fix writing of array property
Only acpi_dp of type DP_TYPE_TABLE is allowed to be an array. This
DP_TYPE_TABLE does not have a value which is written. Thus,
acpi_dp_write_array needs to start counting from the next element type
in the array. Fix this by updating the initialization in for loop for
writing array elements.

BUG=chrome-os-partner:55988
BRANCH=None
TEST=Verified that the correct number of elements are passed for
add_gpio in maxim sdmode-gpio.

Change-Id: I8e1e540d66086971de2edf0bb83494d3b1dbd176
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/16871
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-07 18:04:34 +02:00
Duncan Laurie
02fdb3e014 x86: acpi: Use GOOG ID for coreboot table
Use the GOOG ACPI ID until there is an official ID allocation
for coreboot.  Since I administer this range I allocated
0xCB00-0xCBFF for coreboot use.

Change-Id: I38ac0a0267e21f7282c89ef19e8bb72339f13846
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16724
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-27 16:39:30 +02:00
Duncan Laurie
1f6e681355 x86: acpi: Add function for querying GPE status
Add a function that can be implemented by the SOC to read
and clear the status of a single GPE.  This can be used
during firmware to poll for interrupt status.

BUG=chrome-os-partner:53336

Change-Id: I551276f36ff0d2eb5b5ea13f019cdf4a3c749a09
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16669
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-21 10:46:00 +02:00
Martin Roth
8ea06512e6 Makefiles: update cbfs types from bare numbers to values
These values are found in util/cbfstool/cbfs.h.

Change-Id: Iea4807b272c0309ac3283e5a3f5e135da6c5eb66
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16646
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-21 09:36:11 +02:00
Duncan Laurie
1efcfcfff9 Revert "x86: acpi: Add function for querying GPE status"
This reverts commit 884dfe6329.
2016-09-19 19:20:24 -07:00
Duncan Laurie
884dfe6329 x86: acpi: Add function for querying GPE status
Add a function that can be implemented by the SOC to read
and clear the status of a single GPE.  This can be used
during firmware to poll for interrupt status.

BUG=chrome-os-partner:53336

Change-Id: I536c2176320fefa4c186dabcdddb55880c47fbad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-19 19:03:34 -07:00
Aaron Durbin
1e9a914207 arch/x86,lib: make cbmem console work in postcar stage
Implement postcar stage cbmem console support. The postcar stage
is more like ramstage in that RAM is already up. Therefore, in
order to make the cbmem console reinit flow work one needs the cbmem
init hook infrastructure in place and the cbmem recovery called.
This call is added to x86/postcar.c to achieve that. Additionally,
one needs to provide postcar stage cbmem init hook callbacks for
the cbmem console library to use. A few other places need to
become postcar stage aware so that the code paths are taken.
Lastly, since postcar is backed by ram indicate that to the
cbmem backing store.

BUG=chrome-os-partner:57513

Change-Id: I51db65d8502c456b08f291fd1b59f6ea72059dfd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16619
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-19 17:02:17 +02:00
Aaron Durbin
6b0cebccc4 arch/x86: move postcar main logic into C
The console_init(), MTRR printing, and loading ramstage
logic was previously all in assembly. Move that logic
into C code so that future features can more easily be
added into the postcar boot flow.

BUG=chrome-os-partner:57513

Change-Id: I332140f569caf0803570fd635d894295de8c0018
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16618
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-19 17:01:55 +02:00
Martin Roth
16be0337d9 arch/acpi_ivrs.h: Update 8-byte IVRS entry values
I put in the decimal values for these instead of the hex values.
Instead of running them through a BCD converter, update them to use
the hex values.

Change-Id: I3fa46f055c3db113758f445f947446dd5834c126
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16567
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-09-15 01:43:22 +02:00
Elyes HAOUAS
6b72787d27 src/arch: Improve code formatting
Change-Id: Ic1ca6c2e1cd06800d7eb2d00ac0b328987d022ef
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16434
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
2016-09-12 20:05:30 +02:00
Rizwan Qureshi
e8c2e83973 arch/x86: Utilize additional MTRRs in postcar_frame_add_mtrr
In the current implementation of postcar_frame_add_mtrr,
if provided size is bigger than the base address alignment,
the alignment is considered as size and covered by the MTRRs
ignoring the specified size.
In this case the callee has to make sure that the provided
size should be smaller or equal to the base address alignment
boundary.

To simplify this, utilize additonal MTRRs to cover the entire
size specified. We reuse the code from cpu/x86/mtrr/mtrr.c.

Change-Id: Ie2e88b596f43692169c7d4440b18498a72fcba11
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16509
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:52:27 +02:00
Rizwan Qureshi
b1b44d34e3 arch/x86: Always compile postcar library in romstage
postcar_loader.c has a useful library of funtions for
setting up stack and MTRRs. Make it available in romstage
irrespective of CONFIG_POSTCAR_STAGE for use in stack setup
after Dram init.

The final step of moving the used and max MTRRs on to stack
is moved to a new function, that can be used outside of
postcar phase.

Change-Id: I322b12577d74268d03fe42a9744648763693cddd
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12 19:50:18 +02:00
Martin Roth
d4aa2c4348 include/arch/acpi.h: change IVRS efr field to iommu_feature_info
The field that was previously named 'efr' is actually the iommu feature
info field.  The efr field is a 64-bit field that is only present in
type 11h or type 40h headers that follows the iommu feature info field.

Change-Id: I62c158a258d43bf1912fedd63cc31b80321a27c6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16508
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-07 19:00:32 +02:00
Martin Roth
a66df49e15 x86/acpi.c: use #define for IVRS revision field
The revision field was correct, but the comment was wrong. The revision
1 means that the IVRS table only uses fixed length device entries.
Update the field to use the IVRS revision #define.

Change-Id: I4c030b31e3e3f0a402dac36ab69f43d99e131c22
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16507
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-07 19:00:05 +02:00
Martin Roth
b6a77aa720 arch/x86/include: Add #defines for IVRS tables
I/O Virtualization Reporting Structure (IVRS) definitions from:

AMD I/O Virtualization Technology (IOMMU)
Specification 48882—Rev 2.62—February 2015

Change-Id: I4809856eb922cbd9de4a2707cee78dba603af528
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16506
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-07 18:59:54 +02:00
Antonello Dettori
20c9afa9c7 arch/acpi.h: add #if guard to handle the absence of device_t type
Avoid the inclusion of a function declaration if the argument type
device_t is not defined.

This was not a problem until now because the
old declaration of device_t and the new one overlapped.

Change-Id: I05a6ef1bf65bf47f3c6933073ae2d26992348813
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16404
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-04 05:47:53 +02:00
Elyes HAOUAS
dbf30678ee src/arch: Add required space before opening parenthesis '('
Change-Id: I8a44a58506d7cf5ebc9fe7ac4f2b46f9544ba61a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16287
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-28 18:48:30 +02:00
Elyes HAOUAS
2078e75b00 src/arch: Capitalize CPU and ACPI
Change-Id: I37dfa853c3dbe93a52f6c37941b17717e22f6430
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16277
Reviewed-by: Omar Pakker
Tested-by: build bot (Jenkins)
2016-08-28 18:28:28 +02:00
Duncan Laurie
3731903646 acpi: Generate object for coreboot table region
Generate an object to describe the coreboot table region in ACPI
with the HID "CORE0000" so it can be used by kernel drivers.

To keep track of the "CORE" HID usage add them to an enum and add
a function to generate the HID in AML:  Name (_HID, "CORExxxx")

BUG=chromium:589817
BRANCH=none
TEST=build and boot on chell, dump SSDT to verify contents:

Device (CTBL)
{
    Name (_HID, "CORE0000")  // _HID: Hardware ID
    Name (_UID, Zero)  // _UID: Unique ID
    Method (_STA, 0, NotSerialized)  // _STA: Status
    {
        Return (0x0F)
    }
    Name (_CRS, ResourceTemplate ()  // _CRS: Current Resource Settings
    {
        Memory32Fixed (ReadOnly,
            0x7AB84000,         // Address Base
            0x00008000,         // Address Length
            )
    })
}

Change-Id: I2c681c1fee02d52b8df2e72f6f6f0b76fa9592fb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16056
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-06 04:35:43 +02:00
Werner Zeh
21a5bff77b ACPI: Add code to create root port entry in DMAR table
PCI root ports with "Address Translation Service" capability can be
reported in DMAR table in the ATSR scope to let the OS know how to
handle these devices the right way when VT-d is used.
Add code to create an entry for a PCI root port using the type
"SCOPE_PCI_SUB".

Change-Id: Ie2c46db7292d9f1637ffe2e9cfaf6619372ddf13
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15912
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-03 06:24:17 +02:00
Werner Zeh
d4d76959c0 ACPI: Add code to include ATSR structure in DMAR table
DMAR tables can contain so called "Address Translation Service Reporting"
(ATSR) structure. It is applicable for platforms that support
Device-TLBs and describe PCI root ports that have this ability.
Add code to create this ATSR structure.

In addition, a function to fix up the size of the ATSR
structure is added as this is a new type and using the function
acpi_dmar_drhd_fixup() can lead to confusion.

Change-Id: Idc3f6025f597048151f0fd5ea6be04843041e1ab
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15911
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-03 06:23:11 +02:00
Martin Roth
0cd338e6e4 Remove non-ascii & unprintable characters
These non-ascii & unprintable characters aren't needed.

Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15977
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-01 21:44:45 +02:00
Lee Leahy
049b46270d arch/x86: Enable postcar console
Add a Kconfig value to enable the console during postcar.  Add a call
to console_init at the beginning of the postcar stage in exit_car.S.

TEST=Build and run on Galileo Gen2

Change-Id: I66e2ec83344129ede2c7d6e5627c8062e28f50ad
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16001
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-01 21:40:23 +02:00