Commit Graph

22325 Commits

Author SHA1 Message Date
Aaron Durbin 403fdbc226 lib/cbmem: use globals for non CAR global migration platforms
For CAR platforms which don't migrate globals real globals can
be directly used. This alleviates the need to peform partial
recovery on every cbmem access which in turn acts like all non-CAR
platforms or any stages which execute entirely out of RAM.

Change-Id: I31c08dd6473324424d5d42fe6b56d42fe635929e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03 21:38:26 +00:00
Paul Kocialkowski d85e485c58 libpayload: video: Add support for font scaling with a factor
This introduces support for font scaling with a factor provided via
Kconfig. In practice, the font itself is not scaled at any point in
memory and only the logic to determine whether a pixel should be filled
or not is changed.

Thus, it should not significantly impact either the access time or
memory use.

Change-Id: Idff210617c9ec08c6034aef107cfdb34c7cdf029
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/20709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-03 20:37:07 +00:00
Paul Kocialkowski 1c0b603673 libpayload: video: Introduce helpers for font access
This introduces helpers for accessing the included font, instead of
using hardcoded values provided by the font's header itself.

It will allow painlessly adding support for font scaling in a subsequent
change. It should not introduce any functionality change.

Change-Id: I0277984ec01f49dc51bfc8237ef806f13e3547e2
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/20708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-03 20:34:59 +00:00
Subrata Banik 5a752f7b8f soc/intel/apollolake: Skip disabled IGD device
If IGD PCI device is disabled:
1. BAR for the device will be 0.
2. There is no need to allocate framebuffer for this device.

Some early SOCs don't have GFX model fuse by default hence
we need to add a check to ensure PCI device is enable. This
code to avoid die inside coreboot for missing resources.

Change-Id: Ied677e8c77fa7b166b016da458caad0e4702b5d8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03 20:30:19 +00:00
Subrata Banik d00d682670 soc/intel/skylake: Skip disabled IGD device
If IGD PCI device is disabled:
1. BAR for the device will be 0.
2. There is no need to allocate framebuffer for this device.

Some early SOCs don't have GFX model fuse by default hence
we need to add a check to ensure PCI device is enable. This
code to avoid die inside coreboot for missing resources.

Change-Id: Ic31d3e57ba730f6b569bf2cc3bdc54cb369b8caf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03 20:30:09 +00:00
Iru Cai 4225493159 util/kbc1126: Refactor kbc1126_ec_insert
Add support for setting addresses of blobs only, and using address in
memory when ROM is mapped

Change-Id: I053c55253eee00558071d15923e3eb17b1e8410c
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/20474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-03 18:54:41 +00:00
Lijian Zhao dcf99b0445 soc/intel/cannonlake: Sort Kconfig for Cannonlake
Look and feel update, sort the sequence in Kconfig.

Change-Id: I41d99979d9c7d081086aac8bfef27186b37a6e70
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03 18:54:11 +00:00
Matt DeVillier ea5336d240 soc/intel/braswell/Kconfig: select RELOCATABLE_RAMSTAGE
Without RELOCATABLE_RAMSTAGE selected, S3 resume will hang under
Linux and Windows.  All other Intel SoCs have this selected by
default, so this change simply corrects an omission on Braswell.

TEST: boot Linux on google/cyan with and without RELOCATABLE_RAMSTAGE
selected; observe that S3 resume fails without and succeeds with.

Change-Id: I9071d9b4e3e3a156281d95fae059947c4c26f744
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03 18:51:59 +00:00
Ivy Jian 3a6b0ca60a google/kahlee: Add Realtek audio codec ASL
Add the RT5650 codec ASL for proper Linux driver loading.

Devices visible to OS:
 /sys/bus/acpi/devices/AMDI1002:00
 /sys/bus/acpi/devices/I2SC1002:00

Change-Id: I60b256f68372c9d17d67c9cb2accaca616a0b9a5
Signed-off-by: Ivy Jian <ivy_jian@compal.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-03 18:49:28 +00:00
Felix Held 2adab28ff6 intel/bd82x6x: Replace magic IOBP constants with known names
IOBP (I/O Buffer Programming) is an interface (indirect addresses space)
in the RCBA that is used to configure the high speed serial lanes on the
PCH, that are used for PCIe, USB3 and SATA.

This patch replaces the offsets in RCBA with the defines from pch.h, gives
the access functions and their parameters useful names and replaces two
magic addresses in IOBP space with their defines.

Change-Id: I91a828ed076ca10733b47db876fabf5adaa63638
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/16214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-03 18:47:19 +00:00
Aaron Durbin fb53242716 lib/cbmem: remove cbmem_region_used()
The cbmem_region_used() function wasn't being utilized outside this
module. Threfore, reduce the surface area.

Change-Id: I28a9d02221048ab0aa4cd3d986d17ee7692ce636
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03 16:37:00 +00:00
Aaron Durbin 33e57906f5 lib/imd_cbmem: remove unused #include
Change-Id: I18a08faa5f9f5330cdb509c27a8ab7a3aa8e5b73
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03 16:36:15 +00:00
Aaron Durbin d46b8d581a lib/imd_cbmem: remove unused funciton
The cbmem_fail_recovery() function was no longer used. I'm not sure
why the compiler never complained. Regardless, delete it.

Change-Id: I7d94118068064c61252d1b5ca9d8e92658a699e0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-08-03 16:36:08 +00:00
Patrick Georgi 1ac0aa9c1c soc/nvidia/tegra*: force using our headers instead of compiler's/system's
The code doesn't include much, but when compiled outside the coreboot
build (what the shipped Makefile is made for), we want to make sure that
the few files it includes are controlled by us.

TEST=`cd src/soc/nvidia/tegra124/lp0; make CC=arm-eabi-gcc` works

Change-Id: Ic2f1e4aa4047617b048ef7ef98d71f9d540ccd74
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20860
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-02 18:59:19 +00:00
Patrick Georgi d42eb37be4 util/cbfstool: Fix build with armv7-eabi cross compiler
We recently changed all PACKED, __PACKED, __attribute__((packed)) ... to
__packed to gain some consistency. In cbfstool we use compiler.h to
provide that where necessary.

The cross compiler I use doesn't provide __packed by itself, but liblz4
doesn't compensate for that. Therefore include compiler.h, and to avoid
adding dependencies to non-liblz4 code, do so through the command line.

Change-Id: I581e45639ac3e103af7c16793e8effe2e632dec7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-02 09:55:11 +00:00
Konstantin Aladyshev 8656914cda AGESA: Correct PCI function number for MEM_GET(SET)REG outputs
PCI function number takes only 3 bits, therefore
correct bitmask for it is 0x7.

Change-Id: Id41700be0474eecc4d5b5173c4d5686c421735e3
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-on: https://review.coreboot.org/20837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-02 05:29:03 +00:00
Konstantin Aladyshev 14c8f71b0b AGESA f15: Support DMI generation for Opteron 63XX family
Add support of DMI tables for AMD Opteron 6300 Series Processors.
Correct value for CPU family is taken from SMBIOS reference
specification.

Change-Id: I8c5d487c0f45f61deb081be50c6701a42fbf9111
Signed-off-by: Konstantin Aladyshev <aladyshev22@gmail.com>
Reviewed-on: https://review.coreboot.org/20838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-02 05:28:31 +00:00
Kyösti Mälkki 903ce25040 binaryPI: Introduce BINARYPI_LEGACY_WRAPPER and its counterpart
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.

New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.

For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.

New method is expected to be compatible with binaryPI.

Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 05:11:04 +00:00
Kyösti Mälkki dbd64953ae binaryPI: Add dispatcher for PI blob
Change-Id: I622d155fce3fa56cd5e24282e22de060fed560c3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 05:05:27 +00:00
Kyösti Mälkki bf201d58eb AGESA f15tn f16kb: Implement common FCH callout
This FCH_OEM_CALLOUT bypasses API and uses structures
that are private to AGESA. Attempt to clean it up by
first clarifying when it is used.

Change-Id: I63aa0f586f73e97d615b8596d73728edbaeb0a2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 05:00:27 +00:00
Kyösti Mälkki e95b6b291e binaryPI: Enable RELOCATABLE_RAMSTAGE
Change-Id: I0c0058be002e409bd16d2d75fd404df94407df4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:57:56 +00:00
Kyösti Mälkki 6e37b0acb6 binaryPI: Enable EARLY_CBMEM_INIT
Also moves postcar stack to CBMEM.

Change-Id: I0263af9561e0367bbbde4d5c3190039f4c3047a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19347
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-08-02 04:57:07 +00:00
Kyösti Mälkki c43cd97802 AGESA: Conditionally enable RELOCATABLE_RAMSTAGE
Change-Id: Id199322db077fc5f112dfa45f8e9f72b9142a8fb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:56:10 +00:00
Kyösti Mälkki 7369e83de1 AGESA: Add romstage timestamps
Experiments on f14 f15tn and 16kb suggest that TSC
counter value shifts at end of raminit. To account
for this all previously stored values in timestamp
table are also divided by 4.

Change-Id: I47584997bf456e35cf0aeb97ef255748745c30ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:51:02 +00:00
Kyösti Mälkki fb32be4090 AGESA: Implement EARLY_CBMEM_INIT
Boards without AGESA_LEGACY_WRAPPER gain EARLY_CBMEM_INIT.
This does not apply to family12 and family14 just yet, as
they do invalidate without write-back on CAR teardown.

Change-Id: I008356efa2bc3df0ed1f0720e225ecc7e9995127
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:50:33 +00:00
Kyösti Mälkki a18f58b862 AGESA: Split dispatcher to stages
Change-Id: Ide49e46c0b6aa5e1bf09354435a847a46bc797c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:49:59 +00:00
Kyösti Mälkki 21e609c1c9 AGESA: Move romstage-ramstage splitline
In AGESA specification AmdInitEnv() is to be called once
host memory allocator has started. In coreboot context this
could mean either availability of CBMEM or malloc heap.

As for AmdS3LateRestore(), there is no requirement to have
it run as part of the romstage either.

Change-Id: Icc8d97b82df89e2480e601d5c2e094de0365b0a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:48:20 +00:00
Kyösti Mälkki ed8d2777f8 AGESA binaryPI: Unify agesawrapper header
Change-Id: I54c8553bc057798e595b28f6cbc07f7125ae074f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:48:06 +00:00
Kyösti Mälkki a3d644fcd1 AGESA: Consolidate platform_once() call
Change-Id: I13d8df330db925b2eced7c123ca9926fb259646d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20621
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-08-02 04:46:58 +00:00
Kyösti Mälkki b0931d3d10 AGESA: Consolidate early_all_cores() call
Change-Id: I7c3af493b9189bb75a58eb322646694b5a712745
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:46:36 +00:00
Kyösti Mälkki 28c4d2f7e0 AGESA: Introduce AGESA_LEGACY_WRAPPER and its counterpart
We define AGESA_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.

New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.

For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.

New method is expected to be compatible with binaryPI.

Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:46:29 +00:00
Kyösti Mälkki c7dcec6a1b AGESA: Move agesawrapper_laterunaptask()
Change-Id: I916d808d1b2ecc4b70b5dfebff62c4a18119f157
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:41:14 +00:00
Kyösti Mälkki 0a7cab8de8 AGESA: Refactor eventlog read loop
Also avoid infinite loop.

Change-Id: I7571f9efdc2bf0335788136b8c56e9290581d748
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:40:37 +00:00
Kyösti Mälkki 0e01c4841d AGESA: Use common handler for ACPI tables
Change-Id: I2d6ab1026f1105f1fea97682442a169409248c39
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:39:29 +00:00
Kyösti Mälkki 6cb4ee31ed AGESA: Sync ACPI table definitions
Change-Id: I09b094b3f129ac3e32608bcbe56f4b3f90c8946b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-08-02 04:39:20 +00:00
Martin Roth b08d73b845 src/northbridge: Add guards on all header files
Change-Id: I93b939478615f22f2c078b1efb7999ad4f3a4c28
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-08-01 23:05:52 +00:00
Martin Roth 54cb493f97 src/device: Add guards on all header files
Change-Id: I8641f32ed2221f1d6e6dac884912251f64424f4d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-08-01 23:05:39 +00:00
Martin Roth 1cd303a6fc src/acpi: Add guards on all header files
Change-Id: I1b2d82a85194df6660bc041af8a690acc5469d02
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-08-01 23:04:27 +00:00
Martin Roth 7a4c02145d src/include: Add guards on all header files
Change-Id: I2d7d4e0b25f2cf3eef2040f89d5ebc711909cdd7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-08-01 23:04:15 +00:00
Evelyn Huang 284409fd8c src/cpu/amd/quadcore: Fix checkpatch errors/warnings
Fix over 80 character line warnings, unncessary braces for single
statement blocks warnings, include space before and after =, <, >
warnings, spaces after open parantheses warnings

Change-Id: Ib0a28c12e209547b3625f4ca1696f9c26dc2b6d0
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/19987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-01 23:02:11 +00:00
Evelyn Huang 0182aea283 cpu/amd/pi: Fix checkpatch warnings and errors
Fix remaining space prohibited between function name and open
parenthesis, line over 80 characters, unnecessary braces for single
statement blocks, space required before open brace errors and warnings
in subdirectories of src/cpu/amd/pi

Change-Id: I177ffe98a3674bd700a39eb8073db34adf9499b4
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-08-01 23:01:56 +00:00
Evelyn Huang 67ce5052fe Documentation: Create Lesson2.md
Lesson 2 goes over:
-Setting up an account on gerrit
-Cloning coreboot
-Submiting a commit using git

Change-Id: I756b273cf832fc014ba2077a5a4fe4d8009aae6d
Signed-off-by: Evelyn Huang <evhuang@google.com>
Reviewed-on: https://review.coreboot.org/20212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-01 23:01:08 +00:00
Lin Huang c93d79b6cb google/gru: Correct Scarlet pwm regulator minimum value and maximum value
In Scarlet pwm regulatoror minimum value and maximum value differs from
other board variants, Correct it so we can get the right voltage.

Change-Id: I1f722eabb697b3438d9f4aa29c205b0161eb442a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-01 20:00:25 +00:00
Lin Huang a2c5b2f252 google/gru: Correct the Sdcard control gpio setting for Scarlet
in Scarlet the Sdcard control gpio differs from other
board variants, So set the GPIO to high on Scarlet.

Change-Id: I5fa19b212a716213462eea58b6242392d32a2c5c
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-08-01 20:00:21 +00:00
Lin Huang 05c3e84622 google/gru: Use 1.8V powerdomain for gpio4cd on Scarlet
Scarlet gpio4cd use 1.8V powerdomain, let's make a
correct register setting, otherwise even the uart
does not work.

Change-Id: Ib5a8b2a4d92502fb829688d0a3e1b645d53cd7fc
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2017-08-01 20:00:18 +00:00
Martin Roth 6c581bc43f soc/dmp/vortex86: Fix CMOS read and random RTC reset
The array of CMOS values that was passed into the read routine was
never getting updated.  GCC 7.1 gives a warning on this:

error:  may be used uninitialized in this function

Change-Id: I2f7c9b6455761a38598467b001efb0603fd14c32
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-08-01 13:20:15 +00:00
Martin Roth ba973bd2de util/abuild: Set exit status on failure
Currently, the what-jenkins-does target doesn't stop if abuild fails.
This change gives a command line parameter to abuild with tells it to
exit with a non-zero exit status if any of the builds failed.

This will be particularly useful for concourse which doesn't parse the
junit.xml files, and only knows whether a build passed or failed by the
exit status.

Change-Id: Ic2be5deaedacd3f55db8e0b14a2b7b39cc44664e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@google.com>
2017-07-31 20:52:07 +00:00
Martin Roth 6c1c9d5d5f Update vboot submodule to upstream master
Updating from commit id 04b3835b:
2017-06-12 06:47:41 -0700 - (Add a script to generate a keypair for signing Rose RW firmware.)

to commit id 8b714252:
2017-07-18 02:36:16 -0700 - (crossystem: Remove defunct sw_wpsw_boot field)

This brings in 19 new commits.

Change-Id: Ib68068b1afc5a264623021325e19644e8b63f8f3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-31 20:30:55 +00:00
Martin Roth 8f1e1bd44d Update arm-trusted-firmware submodule to upstream master
Updating from commit id 3944adca:
2017-03-18 12:16:27 +0000 - (Merge pull request #861 from soby-mathew/sm/aarch32_fixes)

to commit id b1187232:
2017-06-20 15:34:54 +0100 - (Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisons)

This brings in 373 new commits.

Change-Id: I653007f664921305d22645f7904bb2d8eb85fe67
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-07-31 20:30:51 +00:00
Marc Jones 0a15ed57c6 google/kahlee: Add mainboard GPIOs to ACPI
Add the Google mainboard GPIOs to the ACPI table.

Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31 17:34:48 +00:00