Initialize and calibrate DRAM in romstage.
DRAM full calibration logs:
dram_init: dram init end (result: 1)
DRAM-K: Full calibration passed in 20014 msecs
TEST=DRAM full calibration pass.
BUG=b:202871018
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I80a18a8be5b1d47a5f0f7afed9601c0884e69035
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Current mainboard code supports different baseboard binding
example: brya uses BOARD_GOOGLE_BASEBOARD_BRYA and brask uses
BOARD_GOOGLE_BASEBOARD_BRASK Kconfig.
This patch makes the `BOARD_GOOGLE_BRYA_COMMON` Kconfig default
`n` and specific baseboard binding Kconfig can select this Kconfig.
It would also avoid adding if clause for specific baseboard binding
Kconfig everytime with introduction of newer mainboard in future.
TEST=Verified CONFIG_BOARD_GOOGLE_BRYA_COMMON=y while building brya
and brya coreboot.rom remains the same.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I754159447e68b8ac2ea21009cc801fc5ba5df56e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This patch ensures ADL-P PCH can get selected by mainboard
variants to accommodate mainboards with ADL-N PCH in future.
TEST=Able to build and boot brya without any Kconfig change.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ifbcd1cd7f8ecafee22d50c3f3f20decc4cc62797
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60378
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Copied from commit df72b18d (mb/google/brya/var/taeko: Set vGPIO reset
type).Due to the vGPIO is not reset when we power on through S5, we
would met MCA when PCIE send L1 request without following Ack.
BUG=b:207070967
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Id0df489fe5513c4975747d52c97cb3ee8e691782
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Lists of changes:
1. Create choice config to let ADL mb variants to pick the desire CAR
setup configuration between NEM and eNEM, where NEM and eNEM Kconfig
have selected its required IA SoC common CAR Kconfig to able to perform
the early boot configuration using CAR.
2. Lists of variants (kano, redrix, and felwinter) to drop
INTEL_CAR_NEM Kconfig select and choose eNEM.
3. Default CAR configuration for ADL mb is still NEM due to still using
older SoC skus without eNEM support enabled.
BUG=b:168820083
TEST=Able to build and boot P2 boards using eNEM mode.
Change-Id: Ibe94e6b82739ec65829859271622d904d75e978d
Signed-off-by: subratabanik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I4de9bc426b92d57d6aabe17cceddf6b6aa444327
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Idb7fcaaa175eb5b6e953ad0d5e2c5757d18838e4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Align with other mainboards and put the baseboard option before the
variants ones.
Change-Id: I314239b6d5abd531ccdcbe4426b2c7956dc9ae45
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I52c79f8958c5c40a258bcc292702154765afc476
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ia9c59917196df8226391765f7dd7b7c5cdad1aee
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Since all variants select the option `BASEBOARD_REEF_LAPTOP`, drop it
and let the common baseboard option select it.
Change-Id: I7f2ffd1e7b9ad2fab500b83c4cc56c9fc2d161ab
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Commit d448f8ce0f (drivers/intel/pmc_mux/
conn: Change usb{23}_port_number fields to device pointers) changed the
way the pmc_mux/conn driver gets the corresponding USB ports from the
devicetree. This change didn't include the corresponding change for the
Taniks and Vell variants of the Google Brya project and the Intel
adlrvp_n_ext_ec board which probably weren't in the tree at the time the
patch referenced above was created. This patch ports the needed change
forward to those boards to fix the build of the upstream tree.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id295cd11fbbfe038534b154215a6de7c1ac13e0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
List of changes:
1. Add separate file for ADL-N GPIOs
2. Configure GPIOs as per the schematics of ADL-N RVP
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0c0ca52d0cc73acfd8503007d5f3d2ad9a48f8ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59937
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Set USB2 port 4 pre emphasis to 15mV for passing USB2 port 4 SI (margin eye diagram).
BUG=b:210755120
TEST=emerge-ambassadorcoreboot chromeos-bootimage; Build local fw and pass to HW for measuring USB2 port 4 eye diagram.
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I8163b2be6c9094eaf08efc0325cf211235556dc8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Run the command below to fix all occurrences.
$ git grep -l 'configuration in bootblock\. \*/' | xargs sed -i 's,configuration in bootblock\. \*/,configuration in bootblock */,'
Change-Id: I84669341e2c8976953284dbaf113da3397857de3
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Remove chromeos_dsdt_generator() calls under mainboard, it
is possible to make the single call to fill \CNVS and
\OIPG without leveraging device operations.
Change-Id: Id79af96bb6c038d273ac9c4afc723437fc1f3fc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Support GL9763E as a eMMC boot disk
BUG=b:210089379
TEST=enable DRIVERS_GENESYSLOGIC_GL9763E and check eMMC on taniks.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Iab0fd88ac88e07a8580426234adc9c21df6c11d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add Kconfig item RT8168_SET_LED_MODE to enable LED customization.
Update the LED settings in devicetree.
BUG=b:193750191
TEST=Try different register values to verify LED feature.
Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com>
Change-Id: If80ace497c7481ce40b55af7e17e12a286aa9164
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add Hynix H9JCNNNCP3MLYR-N6E LP5 DRAM part for vell:
DRAM Part Name ID to assign
H9JCNNNCP3MLYR-N6E 1 (0001)
BUG=b:204284866
TEST=emerge-brya coreboot
Change-Id: I1ec2985fa1f1c488ee3a9c5e34f7b370d16cf98e
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The board ID check for audio codec is no longer required, therefore
remove it.
BUG=b:210705216
TEST=emerge-brya coreboot chromeos-bootimage and check audio function
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: Ifbe838186da2e64737a9ffb557cf324124e79a9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
- Enable Acoustic noise mitigation
- Copied from gimble set slow slew rate VCCIA and VCCGT to 8
BUG=b:206704930
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I156859ce6894a6ed5270fe0242de4aef9656bbeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add the stylus field in fw_config.
Update devicetree and gpio to handle stylus pen detection.
BUG=b:167983049
TEST=Build firmware and check behavior as following:
1) Set the fw_config "bit4=1" for pen present:
Wake up from suspend when pen is removed from the garage.
Present the stylus menu when pen is removed from the garage.
2) Set the fw_config "bit4=0" for pen absent:
Wake up and present menu will not work when pen is removed
form the garage.
Change-Id: I62489bb289b18f9aa0823005224eda3ef5218e03
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60185
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a new port for the ASRock H77 Pro4-M motherboard. It is
microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3
SDRAM.
The port was initially done with autoport. It is quite similar to the
ASRock B75 Pro3-M which is already supported by coreboot.
Working:
- Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120)
- Native RAM initialization with four DIMMs of two different types
- PS/2 combined port (mouse or keyboard)
- Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub)
- PCIe graphics in the PEG slot
- All three additional PCIe slots
- All rear and internal USB2 ports
- All rear and internal USB3 ports with reasonable transfer rates
- All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s)
- All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s)
- Rear eSATA connector (multiplexed with one ASM1061 port)
- Console output on the serial port of the Super I/O
- SeaBIOS 1.15.0 to boot slackware64
- SeaBIOS 1.15.0 to boot Windows 10 (needs VGA BIOS)
- Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`)
- External flashing with flashrom-1.2 and a Raspberry Pi 1
- S3 suspend/resume from either Linux or Windows 10
Not working:
- Booting from the two SATA ports provided by the ASM1061
- Automatic fan control with the NCT6776D Super I/O
Untested:
- VBT (it is included, though)
- Infrared header
Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update the two load line slope settings for the SVID3 telemetry.
AGESA sends these values to the SMU, which accepts them as units
of current. Proper calibration is determined by the AMD SDLE tool
and the Stardust test.
vdd scale: 73457 -> 73331
vdd offset: 291 -> 1893
soc scale: 30761 -> 31955
soc offset: 834 -> 852
BUG=b:207299255
BRANCH=guybrush
TEST=1. emerge-guybrush coreboot
2. pass AMD SDLE/Stardust test
Change-Id: I9c9dd4883fd21a70a1e7a50f25a4f76df1e56bc6
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Add support for Alder lake N LP5 RVP with board ID 0x7.
Since SPD index 7 is unused earlier, ADL-N will use it.
Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
This change adds internal USB camera into devicetree for beadrix.
BUG=b:204882915, b:210772511
BRANCH=None
TEST=Built and checked camera device existence with lsusb
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Iddc58c0d27d5da0fa4652f503f15ebb308be18c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
