This attempts to clean out some dead code which was copy + pasted
into Snow's bootblock.c file, along with some unnecessary headers.
Change-Id: If9f157a52395a047c249a2a6385e0e8ddf310e59
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2291
Tested-by: build bot (Jenkins)
This patch moves ARM core and DRAM timing functions around to simplify
the dependencies for system_clock_init().
The original code was architected such that the system_clock_init()
function called other functions to obtain core and memory timings.
Due to the way memory timing information must be obtained on Snow,
which entails decoding platform-specific board straps, the bottom-
up approach resulted in having the low-level clock init code
implicitly depend on board and vendor-specific info:
main()
->system_clock_init()
-> get_arm_ratios()
-> CPU-specific code
-> clock_get_mem_timings()
-> board_get_revision()
-> read GPIOs (3-state logic)
-> Decode GPIOs in a vendor-specific manner
-> Choose memory timings from module-specific look-up table
...then proceed to init clocks
...come back to main()
The new approach gathers all board and vendor-specific info in a
more appropriate location and passes it into system_clock_init():
main()
-> get_arm_ratios()
-> CPU-specific code
-> get_mem_timings()
-> board_get_config()
-> read GPIOs (3-state logic)
-> Decode GPIOs in a vendor-specific manner
-> Choose memory timings from module-specific look-up table
-> system_clock_init()
...back to main()
Change-Id: Ie237ebff76fc2d8a4d2f4577a226ac3909e4d4e8
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2271
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This gets rid of a bunch of duplicate I2C code in the bootblock.
Change-Id: I51f625a0f738cca4ed2453fbcb78092e4110bc7e
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2289
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This gets rid of a bunch of copy + pasted GPIO code.
Change-Id: I548b2b5d63642a9da185eb7b34f80cbebf9b124f
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2288
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This gets rid of a bunch of copy + pasted code from Exynos UART
files.
Change-Id: I9fbb6d79a40a338c9fdecd495544ff207909fd37
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2286
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Mainboards using `COREBOOT` as their OEM Table ID in their DSDT
header were copied from the same source and therefore had spaces
instead of a tab to align that comment for that header field. These
are mostly Intel based boards.
Fix that in accordance with the coding style [1].
[1] http://www.coreboot.org/Development_Guidelines#Coding_Style
Change-Id: I299b955930dbd50b9717e8ff141ce8f3fd534e5f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2277
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Snow's AP, EC, PMU, and smarty battery share a bus. Both the AP and
EC can act as a master, so to avoid conflicts an arbitration
mechanism consisting of two GPIOs is used.
By default, the AP "owns" the bus unless it is off (in which case
the EC doesn't monitor the arbitration pins). This means the boot
firmware does not need to worry about these lines. The payload may
if it needs to communicate with the EC, though.
In any case, board-specific bus arbitration logic does not belong
in a low-level driver that is supposed to be generic for an entire
CPU family. If the payload needs to talk to the EC, we'll deal with
it there.
Change-Id: I0774d4592af2b21b6ad668441532c5ceab988404
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2272
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This removes some duplicate code from Snow's mainboard bootblock
by utilizing the bootblock build class.
Change-Id: I153247370a8c5127260082dcdca3ebdc5e104fb8
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2270
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
For ARM platform, the bootblock may need more C source files to initialize
UART / SPI for loading romstage. To preventing making complex and implicit
dependency by using #include inside bootblock.c, we should add a new build class
"bootblock".
Also #ifdef __BOOT_BLOCK__ can be used to detect if the source is being compiled
for boot block.
For x86, the bootblock is limited to fewer assembly files so it's not using this
class. (Some files shared by x86 and arm in top level or lib are also changed
but nothing should be changed in x86 build process.)
Change-Id: Ia81bccc366d2082397d133d9245f7ecb33b8bc8b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2252
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
This is a first cut at a romstage. It sets up memory, although that
needs some work; and finds and loads a ramstage.
Change-Id: I02a0eb48828500bf83c3c57d4bacb396e58bf9a5
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2245
Tested-by: build bot (Jenkins)
This replaces the current stage-specific exit/entry functions with
generic versions. Now all stages compile with stage_entry(), which
is placed at .text.stage_entry.armv7, and stage_exit().
Snow's ramstage files are also updated to avoid build breakage.
Change-Id: I953a2c4b8121bd4b66c3362557997a9ca3aa53b0
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2254
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
The SPI flash driver for Exynos chipset.
Verified to boot on snow/armv7.
Change-Id: I7eef67a9c57f825d09f13ea44c2b59b54345fa7b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2229
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Summary:
Isolate CBFS underlying I/O to board/arch-specific implementations as
"media stream", to allow loading and booting romstage on non-x86.
CBFS functions now all take a new "media source" parameter; use
CBFS_DEFAULT_MEDIA if you simply want to load from main firmware.
API Changes:
cbfs_find => cbfs_get_file.
cbfs_find_file => cbfs_get_file_content.
cbfs_get_file => cbfs_get_file_content with correct type.
CBFS used to work only on memory-mapped ROM (all x86). For platforms like ARM,
the ROM may come from USB, UART, or SPI -- any serial devices and not available
for memory mapping.
To support these devices (and allowing CBFS to read from multiple source
at the same time), CBFS operations are now virtual-ized into "cbfs_media". To
simplify porting existing code, every media source must support both "reading
into pre-allocated memory (read)" and "read and return an allocated buffer
(map)". For devices without native memory-mapped ROM, "cbfs_simple_buffer*"
provides simple memory mapping simulation.
Every CBFS function now takes a cbfs_media* as parameter. CBFS_DEFAULT_MEDIA
is defined for CBFS functions to automatically initialize a per-board default
media (CBFS will internally calls init_default_cbfs_media). Also revised CBFS
function names relying on memory mapped backend (ex, "cbfs_find" => actually
loads files). Now we only have two getters:
struct cbfs_file *entry = cbfs_get_file(media, name);
void *data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type);
Test results:
- Verified to work on x86/qemu.
- Compiles on ARM, and follow up commit will provide working SPI driver.
Change-Id: Iac911ded25a6f2feffbf3101a81364625bb07746
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2182
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The previous incarnation did not use all of mmu_setup, which meant
we did not carefully disable things before (possibly) changing them.
This code is tested and works, and it's a bit of a simplification.
Change-Id: I0560f9b8e25f31cd90e34304d6ec987fc5c87699
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2204
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
This patch does a few things to get us into romstage:
- Add romstage as a stage (a later patch adds it as a binary, which
is probably wrong). The Makefile magic is complex enough that we
let it build the XIP file for now, but we no longer use it.
- Replace findstage with loadstage. Loadstage will find a stage,
load the code to memory, and zero the remaining part of memory.
Now we can link the romstage to go anywhere!
- Eliminate magic offsets from code/ldscripts and centralize Kconfig
variables in src/cpu/samsung/exynos5250/Kconfig.
- Tidy up code and serial output
Change-Id: Iae4d2f9e7f429cb1df15d49daf9a08b88d75d79d
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2174
Tested-by: build bot (Jenkins)
This adds a wrapper around main() in romstage which is compiled using
-marm. This assumes that the bootblock branches to romstage in ARM
mode.
The long-term idea is to enforce ABI compatibility when handing off to
the next stage by using shims which are which are compiled in a pre-
determiend manner and leave the main portions of each stage up to
whatever the compiler wants. So it will eventually look like this:
1. bootblock_main (ARM/Thumb)
2. bootblock_exit (ARM)
3. romstage_entry (ARM)
4. romstage_main (ARM/Thumb)
(credit to Gabe Black for writing the patch, I'm just uploading it)
Change-Id: I4fdb8d2c6c2c0a7178bcb9154c378ddce0567309
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/2175
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is the bloated Snow bootblock which includes:
- SPI driver
- UART, including requisite I2C, Maxim PMIC, and clock config code.
- Adjustments for magic offsets (id section, stack pointer address)
This is just a temporary solution until we have romstage loading.
Once that happens, we'll rip out all but the code necessary for
copying SPI ROM content into SRAM.
Change-Id: I2a11e272eb9b6f626b5d9783eabb4a720a1d06be
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2170
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Our earlier attempt was jumping straight from asm to the old u-boot
board_init_f in lowlevel_init_c.c. We are getting ready to transition
to using a real bootblock for ARM, so add romstage.c to the files
compiled and we'll make main() our entry point.
This also updates romstage.ld to place main() (*(.text.startup)) at
the beginning of romstage.
Change-Id: Ifc77a6bfba27d915c4cad62c6c8040665294628a
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2163
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
We don't pass any arguments into romstage on ARM.
Change-Id: I018f28a57fc486c9240345cf0f4043b79027d864
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2162
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This replaces 0x02023400 with an SoC-specific Kconfig variable.
Change-Id: I21482d54a1e1fa6c4437c030ddae2b0bb3331551
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2130
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This mirrors the naming convention of handlers in
northbridge and southbridge.
Change-Id: I45d97c569991c955f0ae54ce909d8c267e9a5173
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2058
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This imports SPL (second phase loader) files from U-Boot. Most of the
content of these files will eventually go away since they're fairly
U-Boot specific. For now they are here to make Jenkins happy.
Change-Id: Ib3a365ecb9dc304b20f7c1c06665aad2c0c53e69
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2081
Tested-by: build bot (Jenkins)
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Fix some minor discrepancies which prevented the MAX77676 from
getting compiled in properly.
Change-Id: Ib29136da6c15a4bdb24926a91729431c507cd209
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2076
Tested-by: build bot (Jenkins)
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is the minimal set of sources that allow the board to build.
These need to be filled in with actual code. But if we get these in upstream
we can stop working against a WIP patch.
Change-Id: I9347a573bb40761f6a12be3ee8febe3ca4be55a3
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2018
Tested-by: build bot (Jenkins)
David Hendricks